k6t1008c2e Samsung Semiconductor, Inc., k6t1008c2e Datasheet - Page 8

• Manufacturer Part Number: k6t1008c2e
• Description: 128kx8 Bit Low Power Cmos Static Ram
• Manufacturer: Samsung Semiconductor, Inc.

DATA RETENTION WAVE FORM
K6T1008C2E Family
CS
CS
TIMING WAVEFORM OF WRITE CYCLE(3)
1
V
4.5V
2.2V
V
CS
GND
2
V
4.5V
CS
V
0.4V
GND
Address
CS
CS
WE
Data in
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS
2. t
3. t
4. t
CC
DR
CC
DR
controlled
controlled
CS
t
in case a write ends as CS
WR
WP
CW
AS
1
2
1
2
2
is measured from the address valid to the beginning of write.
is measured from the end of write to the address change. t
is measured from the begining of write to the end of write.
is measured from the CS
going high and WE going low: A write end at the earliest transition among CS
2
going to low.
1
going low or CS
High-Z
t
SDR
t
t
SDR
AS(3)
1
, a high CS
2
going high to the end of write.
(CS
2
2
Controlled)
and a low WE. A write begins at the latest transition among CS
WR1
Data Retention Mode
Data Retention Mode
8
t
AW
applied in case a write ends as CS
CS V
t
t
WC
CS
CW(2)
t
CW(2)
2
CC
t
WP(1)
0.2V
- 0.2V
1
t
DW
going high, CS
Data Valid
t
WR(4)
t
DH
2
1
going low and WE going high,
or WE going high t
t
RDR
High-Z
t
RDR
CMOS SRAM
WR2
1
goes low,
Revision 3.0
applied
March 2000