gvt71128b18 ETC-unknow, gvt71128b18 Datasheet - Page 3

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gvt71128b18

Manufacturer Part Number
gvt71128b18
Description
128k Synchronous Burst Sram
Manufacturer
ETC-unknow
Datasheet
PIN DESCRIPTIONS
March 4, 1998
Rev. 3/98
37, 36, 35, 34, 33, 32,
100, 99, 82, 81, 80, 48,
47, 46, 45, 44, 49
GALVANTECH
QFP PINS
93, 94
87
88
89
98
92
SYMBOL
A0-A16
WEL#,
WEH#
BWE#
CE2#
GW#
CLK
CE#
VCCQ
VCCQ
VCCQ
VCCQ
VSSQ
VSSQ
DQP2
VSSQ
VSSQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
VCC
DQ9
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
TYPE
Input-
Input-
Input-
Input-
Input-
Input-
Input-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
100 99
31
, INC.
32
98
33
Addresses: These inputs are registered and must meet the setup and hold
times around the rising edge of CLK. The burst counter generates internal
addresses associated with A0 and A1, during burst cycle and wait cycle.
Byte Write Enables: A byte write enable is LOW for a WRITE cycle and
HIGH for a READ cycle. WEL# controls DQ1-DQ8 and DQP1. WEH#
controls DQ9-DQ16 and DQP2. Data I/O are high impedance if either of
these inputs are LOW, conditioned by BWE# being LOW.
Write Enable: This active LOW input gates byte write operations and must
meet the setup and hold times around the rising edge of CLK.
Global Write: This active LOW input allows a full 18-bit WRITE to occur
independent of the BWE# and WEn# lines and must meet the setup and
hold times around the rising edge of CLK.
Clock: This signal registers the addresses, data, chip enables, write
control and burst control inputs on its rising edge. All synchronous inputs
must meet setup and hold times around the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the device and to
gate ADSP#.
Chip Enable: This active LOW input is used to enable the device.
PIN ASSIGNMENT (Top View)
97
34
96
35
95
36
94
37
100-pin PQFP
100-pin TQFP
93
38
128K X 18 SYNCHRONOUS BURST SRAM
92
39
91
40
or
90
41
3
89
42
88
43
87
44
86
45
DESCRIPTION
85
46
84
47
83
48
82
49
81
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Galvantech, Inc. reserves the right to change products or specifications without notice.
NC
VCCQ
NC
A10
NC
VSSQ
NC
DQP1
DQ8
DQ7
VSSQ
VCCQ
DQ6
DQ5
VSS
NC
VCC
ZZ
DQ4
DQ3
VCCQ
VSSQ
DQ2
DQ1
NC
NC
VSSQ
VCCQ
NC
NC
GVT71128B18
PRELIMINARY

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