w39l040a Winbond Electronics Corp America, w39l040a Datasheet
w39l040a
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w39l040a Summary of contents
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... DQ7: #Data Polling...........................................................................................................8 6.4.2 DQ6: Toggle Bit................................................................................................................9 6.5 Table of Operating Modes .............................................................................................. 9 6.5.1 Device Bus Operations.....................................................................................................9 6.5.2 Auto-select Codes (High Voltage Method) .......................................................................9 6.5.3 Sector Address Table .....................................................................................................10 6.5.4 Command Definitions .....................................................................................................10 6.6 Embedded Programming Algorithm ............................................................................. 11 6.7 Embedded Erase Algorithm.......................................................................................... 12 W39L040A Data Sheet 512K × 8 CMOS FLASH MEMORY Publication Release Date:April 14, 2005 - 1 - Revision A3 ...
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... Sector Erase Timing Diagram ...................................................................................... 20 8.6 #Data Polling Timing Diagram ...................................................................................... 20 8.7 Toggle Bit Timing Diagram ........................................................................................... 21 9. ORDERING INFORMATION .................................................................................................... 22 10. HOW TO READ THE TOP MARKING...................................................................................... 23 11. PACKAGE DIMENSIONS ......................................................................................................... 24 11.1 32L PLCC ..................................................................................................................... 24 11.2 32L PDIP....................................................................................................................... 24 11.3 32L TSOP ( mm)................................................................................................. 25 11.4 32L STSOP ( mm) .............................................................................................. 25 12. VERSION HISTORY ................................................................................................................. W39L040A ...
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... GENERAL DESCRIPTION The W39L040A is a 4Mbit, 3V/3.3V CMOS flash memory organized as 512K × 8 bits. For flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes. The byte-wide (× 8) data appears on DQ7 − DQ0. The device can be programmed and erased in-system with a standard 3 ...
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... A0 − A18 A17 A14 A13 DQ0 − DQ7 A8 A9 A11 #CE #OE A10 #OE #CE DQ7 #WE DQ6 DQ5 V DQ4 DQ3 W39L040A OUTPUT CONTROL BUFFER A0 CORE . DECODER ARRAY . PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply DD ...
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... Read Mode The read operation of the W39L040A is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used to gate data from the output pins ...
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... DAH) and byte 1 ( device identifier code (W39L040A = D6hex). All identifiers for manufacturer and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the Auto-select, A1 must be low state ...
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... The operation is initiated by writing the auto-select command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of DAH. A read cycle from address XX01H returns the device code (W39L040A = D6hex). To terminate the operation necessary to write the auto-select exit command sequence into the register ...
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... Write Operation Status 6.4.1 DQ7: #Data Polling The W39L040A device features #Data Polling as a method to indicate to the host that the embedded algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a " ...
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... DQ6: Toggle Bit The W39L040A also features the "Toggle Bit" method to indicate to the host system that the embedded algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling) data from the device at any address will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempt ...
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... AA 2AAA 55 5555 A0 AA 2AAA 55 5555 90 AA 2AAA 55 5555 W39L040A ADDRESS 00000h − 0FFFFh 64 10000h − 1FFFFh 64 20000h − 2FFFFh 64 30000h − 3FFFFh 64 40000h − 4FFFFh 64 50000h − 5FFFFh 64 60000h − 6FFFFh 64 70000h − 7FFFFh 64 Addr. Data Addr. ...
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... Embedded Programming Algorithm Increment Address Program Command Sequence (Address/Command): Start Write Program Command Sequence (see below) #Data Polling/ Toggle bit No Last Address ? Yes Programming Completed 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data Publication Release Date: April 14, 2005 - 11 - W39L040A Pause T BP Revision A3 ...
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... Chip Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH 2AAAH/55H 5555H/10H Start (see below) #Data Polling or Toggle Bit Successfully Completed Erasure Completed Individual Sector Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH 2AAAH/55H Sector Address/30H - 12 - W39L040A Pause SEC PEC ...
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... Read Byte (DQ0 - DQ7) Address = Don't Care Yes DQ6 = Toggle ? No Pass - 13 - W39L040A = Any of the sector addresses within the sector being erased during sector erase operation = Any of the device addresses being erased during chip erase operation Publication Release Date: April 14, 2005 Revision A3 ...
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... min -100 μ min 25° MHz) A SYMBOL CONDITIONS OUT OUT - 14 - W39L040A RATING UNIT ° +70 °C -65 to +150 -0 +0 -0.5 to +4.0 V -0.5 to +12.5 V LIMITS UNIT MIN. TYP. MAX ...
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... AC Test Load and Waveform (Including Jig and Scope 3.0V <5 nS 1.5V/1.5V 1 TTL Gate C = 30pF for 70nS/ 100pF for 90nS L +3.3V 1.2K D OUT 30 pF for 70nS 100 pF for 90nS 2.1K Input Output 3V 1.5V 1.5V 0V Test Point Test Point - 15 - W39L040A CONDITIONS Ω Ω Publication Release Date: April 14, 2005 Revision A3 ...
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... WPH 200 4 and (b) low level signal's reference level W39L040A 90 nS UNIT MAX. MIN. MAX UNIT MIN. TYP. MAX. 90 ...
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... Toggle Bit Output Delay SYMBOL T . READ WRITE SYM. MIN. MAX OEP CEP OET CET Publication Release Date: April 14, 2005 - 17 - W39L040A TYPICAL UNIT μS 100 UNIT MIN. MAX Revision A3 ...
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... V IH #WE High-Z DQ7-0 8.2 #WE Controlled Command Write Cycle Timing Diagram Address A18-0 #CE #OE #WE DQ7 OLZ T CLZ T OH Data Valid OES Data Valid - 18 - W39L040A T OHZ T CHZ High-Z Data Valid OEH T WPH T DH ...
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... T T OES High Z Six-byte code for 3.3V-only software chip erase 5555 5555 2AAA WPH SB2 SB3 SB1 - 19 - W39L040A T CPH CP T OEH T DS Data Valid T DH 2AAA 5555 Internal Erase starts SB4 SB5 Publication Release Date: April 14, 2005 ...
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... Polling Timing Diagram Address A18-0 #WE #CE #OE DQ7 Six-byte commands for 3.3V-only Sector Erase 5555 5555 2AAA WPH SB2 SB3 SB1 CEP T OEH T OEP W39L040A SA 2AAA Internal Erase starts SB4 SB5 OES X X ...
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... Timing Waveforms, continued 8.7 Toggle Bit Timing Diagram Address A18-0 #WE #CE #OE DQ6 T OEH W39L040A T OES Publication Release Date: April 14, 2005 Revision A3 ...
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... W39L040AT90B 90 W39L040A70B 70 W39L040A90B 90 W39L040AT70Z 70 W39L040AT90Z 90 W39L040AP70Z 70 W39L040AP90Z 90 Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. ...
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... HOW TO READ THE TOP MARKING Example: The top marking of 32-pin TSOP W39L040AT-70 W39L040AT70B 2138977A-A12 325OBFA st 1 line: Winbond logo nd 2 line: the part number: W39L040AT70B rd 3 line: the lot number th 4 line: the tracking code: 325 325: Packages made in '03, week 25 O: Assembly house ID: A means ASE, O means OSE, ...etc revision ...
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... Base Plane Seating Plane W39L040A Dimension in Inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. A 0.140 3.56 A 0.020 0. 0.105 0.110 0.115 2.67 2.80 2. 0.026 0.032 0.66 0.81 0.028 ...
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... 11.4 32L STSOP ( mm θ W39L040A Dimension in Inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max 1.20 0.047 0.002 0.006 0.05 0. 0.95 0.037 0.039 0.041 1.00 1.05 ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. PAGE DESCRIPTION - Initial Issued Added 32L PDIP and 32L TSOP package 3, 24, 25 dimensions 26 Add important notice Important Notice - 26 - W39L040A ...