k6r4004c1d Samsung Semiconductor, Inc., k6r4004c1d Datasheet - Page 6

• Manufacturer Part Number: k6r4004c1d
• Description: 1m X 4 Bit High-speed Cmos Static Ram
• Manufacturer: Samsung Semiconductor, Inc.

TIMING DIAGRAMS
K6R4004C1D
WRITE CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End of Write to Output Low-Z
TIMING WAVEFORM OF READ CYCLE(1)
TIMING WAVEFORM OF READ CYCLE(2)
Address
CS
OE
Data out
V
Current
CC
Address
Data Out
Parameter
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
4. At any given temperature and voltage condition, t
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=V
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
levels.
device.
HZ
and t
I
I
CC
SB
OHZ
High-Z
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
Previous Valid Data
Symbol
t
t
t
t
t
t
t
t
t
WP1
WHZ
t
t
WC
CW
WP
WR
DW
OW
AW
DH
AS
t
PU
t
LZ(4,5)
Min
(Address Controlled
(WE=V
t
10
10
OLZ
7
0
7
7
0
0
5
0
3
50%
K6R4004C1D-10
t
OH
t
AA
t
IL.
CO
IH
)
t
OE
- 6 -
HZ
t
AA
(Max.) is less than t
Max
,
t
RC
CS=OE=V
5
-
-
-
-
-
-
-
-
-
-
t
RC
IL
, WE=V
Valid Data
LZ
(Min.) both for a given device and from device to
Min
IH
12
12
8
0
8
8
0
0
6
0
3
)
K6R4004C1D-12
Valid Data
PRELIMINARY
50%
t
PD
CMOS SRAM
Max
6
t
t
-
-
-
-
-
-
-
-
-
-
t
HZ(3,4,5)
DH
OHZ
July 2004
Unit
Rev. 2.0
OH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
or V
OL