adc-321 C&D Technologies., adc-321 Datasheet - Page 3

• Manufacturer Part Number: adc-321
• Description: 8-bit, 50mhz Video A/d Converter
• Manufacturer: C&D Technologies.

TECHNICAL NOTES
1. The ADC-321 is a monolithic CMOS device. It should be
2. It has separate power supply terminals +AV
3. The ADC-321 has separate grounds, the analog GND (pins
4. Bypass all power lines to GND with 0.1µF ceramic chip
5. Even though the analog input capacitance is a low 15pF, it is
6. Apply +2.5V to V
handled carefully to prevent static charge pickup.
and 20) and +DV
circuits. It is recommended that both +AV
powered from a single source
Other external digital circuits must be powered with a
separate +DV
could induce latch up when power is turned on if separate
supplies are used. The operating range of +DV
+3.0V to +5.5V and it allows the use of a common power
supply with 3.3V digital systems. The +3.3V power for +DV
in this case should be taken or derived from the +AV
to avoid latch up. No power supply terminal should be left
open.
22 and 23) and digital GND (pins 28 and 31). Separate and
substantial AGND and DGND ground planes are required.
These grounds have to be connected to one earth point
underneath the device. Digital returns should not flow through
analog grounds. Connect all ground lines to the power point.
capacitors as close to the device as possible. This is
very important.
recommended that high frequency input be provided via a
high-speed buffer amplifier. A parasitic oscillation may be
generated when a high-speed amplifier is used. A 33 ohm
resistor inserted between the output of an amplifier and the
analog input of the ADC-321 will improve the situation. Kick
back noise from A/D CLOCK pulses will be observed at the
analog input terminal, but this has no influence on the ADC-
321 performance.
(pin 24 reference bottom) to obtain an analog input range of
+0.5V to +2.5V. Conversion accuracy is dependent on stable
reference voltages. Provide reference inputs via amplifiers
that have enough driving power to avoid noise problems.
Keep to the following equations;
The ADC-321 has a self bias function which allows the
device to work without external references. Connect V
(pin 17, self bias top) to +AV
bottom) to the analog GND to obtain an analog input range of
+0.56 to +2.48V. Typical voltages at V
®
0V V
RB
S
. A time lag between the two power supplies
S
RT
V
(pin 10) for the internal analog and digital
RT
(pin 18, reference top) and 0.5V to V
+2.7V,
®
S
and V
| V
RBS
RT
RT
– V
(pin 25, self bias
(pin 18) and V
S
RB
and +DV
S
(pins 16, 19
|
S
is from
1.7V
S
S
be
RB
supply
RTS
RB
(pin
S
3
7. A voltage up to +AV
8. Layout A/D CLOCK pulse input (pin 12) as short as possible
9. Digital output is 3-state. To enable 3-state outputs connect
10. The 50MHz sampling rate is guaranteed. It is not recom-
11. The ADC-321 has a clamp function. This clamp is enabled
12. The TEST 1 and 2 (pins 9 and 11) are not used. Always
24) will then be +2.48V and +0.56V respectively. Under an
application where this self bias function is used, the effects of
temperature changes are minimal. Voltage changes of the
+5V supply have direct influence on the performance of the
device. The use of external references is recommended for
applications sensitive to gain error, no ac signals can be
used as references for this device.
input even when +3.3V is powered to +DV
output voltage never exceeds +DV
for minimum influence on other signals. Use of a 100 ohm
series resistor is recommended to protect the device as
there may be some voltage difference and turn-on-time lag
on the power supplies. Analog inputs signals are sampled at
the falling edge of an A/D CLOCK pulse and digital data
become available at the rising edge of an A/D CLOCK pulse
that is delayed by 2.5 clock cycles. The A/D CLOCK are
positive pulse that have 50% duty cycle. The minimum clock
pulse width is 10 nsec for both high and low levels. Keep it
low level while A/D conversions
are on hold.
the OUTPUT ENABLE (pin 30) to GND. To disable, connect
it to +DV
buffered through output registers. The device may be
damaged if a voltage higher than +DV
digital output pins while at high impedance level.
mended to use this device at sampling rates slower than
500kHz because the droop characteristics of the internal
sample and hold exceed the limit required to maintain the
specified accuracy of the device. Also, burst mode sampling
is not recommended.
when CLAMP ENABLE (pin 29) is tied to GND and is
disabled when tied to +DV
(pin 15) are effective when this clamp function is enabled and
signals are clamped whole, this clamp pulse is low. The
clamp reference input (pin 26) is set by an external trim. The
CCP terminal (pin 27) integrates the clamp control voltage
across an external capacitor. Refer to Figure 4 for examples
of various ways to use this clamp function.
leave them open.
S
. The output is recommended to be latched and
S
+ 0.5V can be applied to each digital
S
or left open. Clamp pulse inputs
S
.
S
+ 0.5V is given to
S
, but the digital
ADC-321