adc-321 C&D Technologies., adc-321 Datasheet - Page 4

• Manufacturer Part Number: adc-321
• Description: 8-bit, 50mhz Video A/d Converter
• Manufacturer: C&D Technologies.

ADC-321
THEORY OF OPERATION
(See Functional Block Diagram, Figure 1, and Timing
Diagrams, Figure 2)
1. The DATEL ADC-321 is a 2-step parallel A/D converter
2. This converter uses an offset cancelation type comparator
3. The operation of the respective parts is as indicated in
featuring a 4-bit upper comparator group and two 4-bit
lower comparator groups, each with built-in sample and
hold. A reference voltage equal to the voltage between
(V
comparator block. A voltage corresponding to the upper
data is fed through the reference supply to the lower data.
V
V
bottom) voltages.
and operates synchronously with the external clock. It
features various operating modes which are shown in the
Timing Diagram (Figure 2) by the symbols S, H and C.
These characters stand for Input Sampling (Auto Zero)
Mode, Input Hold Mode and Comparison Mode.
Figure 2-3. For instance, input voltage N is sampled with
the falling edge of the first clock by means of the upper
RTS
RT
RT
(reference voltage top) and V
– V
and V
RB
)/16 is constantly applied to the 4-bit upper
RBS
pins provde the self generation function for
OUTPUTS
OUTPUT 1
OUTPUT 2
OE INPUT
DATA
RB
CLOCK 1.3V
(reference voltage
0. 7 DV
0. 3 DV
tr = 4.5ns
S
S
t
Figure 2-2. ADC-321 Timing Diagram
t
phz
plz
Figure 2-1. ADC-321 Timing Diagram
tr = 4ns
1.3V
t
t
pLH
pHL
90%
10%
tf = 4ns
90%
90%
10%
tr = 4.5ns
4
t
t
pzl
pzh
10%
comparator block and the lower comparator A block. Input
voltage N+1 is sampled with the falling edge of the second
clock by means of the upper comparator block and lower
comparator B block. The upper comparator block finalizes
comparison data UD(N) with the rising edge of the second
clock. The lower comparator block finalizes comparison
data LD(N) with the rising edge of the third clock. UD(N)
and LD(N) are combined and routed to the output as Output
Data N with the rising edge of the fourth clock. Thus there
is a 2.5 clock delay from the analog input sampling point to
the digital data output.
+7.812mV
+0.9922V
+1.9922V
+1.000V
+1.500V
1.3V
1.3V
V
0V
IN
Table 2: Digital Output Coding
V
V
V
V
3V
0V
OH
OL
OH
OL
/(=DGND)
/(=DGND)
0 0 0 0
0 0 0 0
0 1 1 1
1 0 0 0
1 1 0 0
1 1 1 1
3V
0V
MSB
OUTPUT CODE
®
0 0 0 0
0 0 0 1
1 1 1 1
0 0 0 0
0 0 0 0
1 1 1 1
LSB
®