k7a803600m Samsung Semiconductor, Inc., k7a803600m Datasheet - Page 2

• Manufacturer Part Number: k7a803600m
• Description: 256kx36 & 512kx18 Synchronous Sram
• Manufacturer: Samsung Semiconductor, Inc.

K7A803600M
K7A801800M
LOGIC BLOCK DIAGRAM
ADSC
256Kx36 & 512Kx18-bit Synchronous Pipelined Burst SRAM
FEATURES
FAST ACCESS TIMES
ADSP
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
• Three Chip Enables for simple depth expansion with No Data
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A / 119BGA(7x17 Ball Grid Array Package)
Cycle Time
Clock Access Time
Output Enable Access Time
DQPa ~ DQPd
(x=a,b,c,d or a,b)
DQa
WEx
or 2.5V+0.4V/-0.125V for 2.5V I/O
ADV
CLK
LBO
Contention only for TQFP ; 2cycle Enable, 1cycle Disable.
burst.
CS
CS
CS
GW
BW
OE
ZZ
1
2
2
0
PARAMETER
~ DQd
7
or DQa0 ~ DQb7
DQPa,DQPb
Symbol -20 -16 -15 -14 -10 Unit
t
CYC
t
t
CD
OE
BURST CONTROL
5.0 6.0 6.7 7.2 10
3.1 3.5 3.8 3.8 4.5 ns
3.1 3.5 3.8 3.8 4.5 ns
CONTROL
LOGIC
LOGIC
or A
A
0
0
~A
~A
17
18
256Kx36 & 512Kx18 Synchronous SRAM
ns
- 2 -
ADDRESS
REGISTER
A
0
GENERAL DESCRIPTION
~A
1
The K7A803600M and K7A801800M are 9,437,184-bit Syn-
chronous Static Random Access Memory designed for high
performance second level cache of Pentium and Power PC
based System.
It is organized as 256K(512K) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high perfor-
mance cache RAM applications; GW, BW, LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated inter-
nally in the system s burst sequence and are controlled by
the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(lin-
ear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A803600M and K7A801800M are fabricated using
SAMSUNG s high performance CMOS technology and is
available in a 100pin TQFP and 119BGA package. Multiple
power and ground pins are utilized to minimize ground
bounce.
ADDRESS
COUNTER
BURST
or A
A
2
2
~A
~A
A
1
0
17
18
high, ADSP is blocked to control signals.
~A
1
REGISTER
OUTPUT
BUFFER
256Kx36 , 512Kx18
MEMORY
ARRAY
REGISTER
DATA-IN
March 2000
Rev 6.0