k4x56323pg Samsung Semiconductor, Inc., k4x56323pg Datasheet - Page 18
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k4x56323pg
Manufacturer Part Number
k4x56323pg
Description
8m X32 Mobile-ddr Sdram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.K4X56323PG.pdf
(23 pages)
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Note :
1. OP Code : Operand Code. A0 ~ A11 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2.EMRS/ MRS can be issued only at all banks precharge state.
3. Auto refresh functions are same as the CBR refresh of DRAM.
4. BA0 ~ BA1 : Bank select addresses.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
K4X56323PG - 7(8)E/G
Command Truth Table
Register
Refresh
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Deep Power Down
Burst Stop
Precharge
Active Power Down
Precharge Power Down
DM
No operation (NOP) : Not defined
A new command can be issued 2 clock cycles after EMRS or MRS.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
COMMAND
Mode Register Set
Auto Refresh
Self
Refresh
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
All Banks
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
Entry
Entry
Entry
Entry
Exit
Exit
Exit
Exit
CKEn-1 CKEn
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
X
X
X
X
X
X
X
L
L
L
L
CS
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS
H
X
H
H
H
X
H
X
V
X
X
H
X
V
X
H
L
L
L
L
X
CAS
H
H
H
H
H
H
H
L
X
X
X
V
X
X
X
V
X
L
L
L
WE
H
H
X
H
H
X
X
V
X
X
H
X
V
X
H
L
L
L
L
L
Mobile-DDR SDRAM
BA0,1
V
V
V
X
V
A10/AP
OP CODE
H
Row Address
H
H
L
L
L
X
X
X
X
X
X
X
X
A9 ~ A0
Address
(A0~A8)
Address
(A0~A8)
Column
Column
A11,
January 2006
X
Note
1, 2
4, 6
3
3
3
3
4
4
4
7
5
8
9
9