mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 139

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

3.2.3.9
The CC provides two timers with timer interrupt configuration registers for setting interrupts for specific
points of global time. Each timer contains two parameters:
3.2.3.9.1
Address 0x30
Reset
This register holds base cycle and cycle repetition values for timer 0.
A hard reset clears the register.
BCT[0:5]
Base cycle value for timer 0.
CR[0:2]
Cycle repetition value for timer 0.
Freescale Semiconductor
Reserved
Reserved
1. Cycle Set: A 9-bit register is used to specify in which set of communication cycles the interrupt
2. Macrotick Offset: This 16-bit value is the macrotick offset from the beginning of the cycle in
15
7
r
r
will occur. It consists of two fields, the base cycle [b] and the cycle repetition [c]. The set of cycle
numbers where the interrupt is to generated is determined from these two fields using the formula:
where:
— b is a 6-bit cycle number used to identify the initial value for generating the cycle set.
— c is a 3-bit value used to determine a constant repetition factor to be added to the base cycle
— b must be smaller than 2^c:
which the interrupt is to occur. The interrupt occurs at this offset for each cycle in the interrupt
cycle set.
0x0
(c = 0 … 6)
Timer Related Registers
Timer Interrupt Configuration Register 0 Cycle Set (TICR0CS)
Reserved
Reserved
14
6
r
r
Figure 3-115. Timer Interrupt Configuration Register 0 Cycle Set
Reserved
BCT5
13
rw
5
r
b + n*2^c (n = 0, 1, 2, …)
MFR4200 Data Sheet, Rev. 0
Reserved
BCT4
b<2^c.
12
rw
4
r
Reserved
BCT3
11
rw
3
r
BCT2
CR2
10
rw
rw
2
Memory Map and Registers
BCT1
CR1
rw
rw
9
1
Eqn. 3-13
Eqn. 3-14
BCT0
CR0
rw
rw
8
0
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