HFA3783IN96 INTERSIL [Intersil Corporation], HFA3783IN96 Datasheet - Page 11

• Manufacturer Part Number: HFA3783IN96
• Description: I/Q Modulator/Demodulator and Synthesizer
• Manufacturer: INTERSIL [Intersil Corporation]

PLL Synthesizer and DC Offset Clock Programming Table
NOTES:
Reference Frequency Counter/Divider
LO Frequency Counters/Dividers
Operational Modes
Operational
Mode
Offset
Calibration
6. The Serial data is clocked on the Rising Edge of the serial clock, MSB first. The serial Interface is active when LE is LOW. The serial Data is
7. The M register or Operational Mode needs to be loaded first. Registers R, A/B and Offset Calibration follow M loading in any sequence.
SERIAL
BITS
latched into defined registers on the rising edge of LE.
R(0-14)
B(0-10)
A(0-6)
M(13)
M(14)
M(15)
M(0)
M(2)
M(3)
M(4)
M(5)
M(6)
M(7)
M(8)
BIT
BIT
BIT
LSB 1
DEFINITION
REGISTER
1
1
Least significant bit R(0) to most significant bit R(14) of the divide by R counter. The Reference signal frequency is divided down
by this counter and is compared with a divided LO by a phase detector.
Least significant bit A(0) to most significant bit A(6) of a 7-bit Swallow counter and LSB B(0) to MSB B(10) of the 11 bits divider.
The LO frequency is divided down by [P
compared by a phase detector with the divided Reference signal.
(PLL_PE), Phase Lock Loop Power Enable. 1 = Enable, 0 = Power Down. Serial port always on.
Prescaler Select. 0 = 16/17, 1 = 32/33
Charge Pump Current Setting.
Charge Pump Sign.
LD Pin Multiplex Operation.
Charge Pump Operation/Test.
2
0
1
M(0)
C(0) C(1) C(2) C(3) C(4) C(5) C(6)
3
11
4
0
M(2) M(3) M(4) M(5) M(6) M(7) M(8)
5
6
7
M(13)
M(15)
M(6)
*
0
0
0
0
1
1
1
0
0
1
1
B+A], where P is the prescaler divider set by bit M(2). This divided signal frequency is
8
HFA3783
9
10
0
M(14)
DESCRIPTION
DESCRIPTION
DESCRIPTION
M(4)
M(5)
M(8)
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
11
0
(Continued)
12
0
0
Source Current if LO/ [P
Source Current if LO/ [P
Normal Operation
Charge Pump Constant Current Source
Charge Pump Constant Current Sink
High Impedance State
13
0
0
C(11)
14
M(3)
M(7)
0
X
X
X
0
1
0
1
0
1
15
OPERATION/TEST
0
*
*
M(13) M(14) M(15)
B+A] < Ref/R
B+A] > Ref/R
16
0.25mA
0.50mA
0.75mA
1.00mA
Lock Detect Operation
Short to GND
Serial Register Read Back
Ref. Divided by R Waveform
LO Divided by [P
Waveform
X (Don’t Care)
OUTPUT SINK/SOURCE
17
OUTPUT AT PIN LD
18
*
19
B+A]
X
MSB
X