A43E16161V-75F AMICC [AMIC Technology], A43E16161V-75F Datasheet - Page 19
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A43E16161V-75F
Manufacturer Part Number
A43E16161V-75F
Description
1M X 16 Bit X 2 Banks Low Power Synchronous DRAM
Manufacturer
AMICC [AMIC Technology]
Datasheet
1.A43E16161V-75F.pdf
(46 pages)
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8. Burst Stop & Precharge Interrupt
9. MRS
PRELIMINARY
Note : 1. t
DQ(CL2)
DQ(CL3)
2. t
3. Number of valid output data after Row precharge or burst stop : 1,2 for CAS latency=2,3 respectively.
4. PRE : Both banks precharge if necessary.
1) Write Interrupted by Precharge (BL=4)
3) Read Interrupted by Precharge (BL=4)
MRS can be issued only at all bank precharge state.
Mode Register Set
RDL
BDL
CMD
DQM
CMD
CMD
CLK
DQ
CLK
CLK
(August, 2005, Version 0.0)
: 1CLK, Last Data in to Burst Stop Delay.
: 2CLK, Last Data in to Row Precharge.
PRE
WR
D0
RD
Note 4
D1
t
RP
PRE
t
D2
Q0
RDL
PRE
MRS
Q0
D3
Q1
Note 1
1CLK
Note 3
1
ACT
Q1
2
18
DQ(CL2)
DQ(CL3)
2) Write Burst Stop (BL=8)
4) Read Burst Stop (BL=4)
CMD
CMD
CLK
CLK
DQ
WR
RD
D0
AMIC Technology, Corp.
D1
STOP
Q0
D2
t
BDL
STOP
Q0
(note 2)
Q1
A43E16161
Note 3
1
Q1
2
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