CC2530F128 APLUS [Aplus Intergrated Circuits], CC2530F128 Datasheet - Page 9

• Manufacturer Part Number: CC2530F128
• Description: A True System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee Applications
• Manufacturer: APLUS [Aplus Intergrated Circuits]

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ADC CHARACTERISTICS
T
(1) Measured with 300-Hz sine-wave input and VDD as reference.
Copyright © 2009, Texas Instruments Incorporated
ENOB
THD
CMRR
DNL
INL
SINAD
(–THD+N)
A
= 25°C and VDD = 3 V, unless otherwise noted.
(1)
(1)
(1)
(1)
(1)
..........................................................................................................................................................
Input voltage
External reference voltage
External reference voltage differential
Input resistance, signal
Full-scale signal
Effective number of bits
Useful power bandwidth
Total harmonic distortion
Signal to nonharmonic ratio
Common-mode rejection ratio
Crosstalk
Offset
Gain error
Differential nonlinearity
Integral nonlinearity
Signal-to-noise-and-distortion
Conversion time
Power consumption
Internal reference voltage
PARAMETER
(1)
Product Folder Link(s):
(1)
CC2530F32 CC2530F64 CC2530F128 CC2530F256
VDD is voltage on AVDD5 pin
VDD is voltage on AVDD5 pin
VDD is voltage on AVDD5 pin
Using 4-MHz clock speed
Peak-to-peak, defines 0 dBFS
Single-ended input, 7-bit setting
Single-ended input, 9-bit setting
Single-ended input, 10-bit setting
Single-ended input, 12-bit setting
Differential input, 7-bit setting
Differential input, 9-bit setting
Differential input, 10-bit setting
Differential input, 12-bit setting
7-bit setting, both single and differential
Single-ended input, 12-bit setting, –6 dBFS
Differential input, 12-bit setting, –6 dBFS
Single-ended input, 12-bit setting
Differential input, 12-bit setting
Single-ended input, 12-bit setting, –6 dBFS
Differential input, 12-bit setting, –6 dBFS
Differential input, 12-bit setting, 1-kHz sine (0
dBFS), limited by ADC resolution
Single-ended input, 12-bit setting, 1-kHz sine (0
dBFS), limited by ADC resolution
Midscale
12-bit setting, mean
12-bit setting, maximum
12-bit setting, mean
12-bit setting, maximum
Single-ended input, 7-bit setting
Single-ended input, 9-bit setting
Single-ended input, 10-bit setting
Single-ended input, 12-bit setting
Differential input, 7-bit setting
Differential input, 9-bit setting
Differential input, 10-bit setting
Differential input, 12-bit setting
7-bit setting
9-bit setting
10-bit setting
12-bit setting
CC2530F32, CC2530F64, CC2530F128, CC2530F256
TEST CONDITIONS
SWRS081A – APRIL 2009 – REVISED APRIL 2009
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MIN
0
0
0
0–20
TYP MAX
2.97
10.8
10.0
11.5
–75.
–86.
70.2
79.3
78.8
88.9
0.68
0.05
13.3
35.4
46.8
57.5
66.6
40.7
51.6
61.8
70.8
1.15
>84
>84
197
132
5.7
7.5
9.3
6.5
8.3
0.9
4.6
1.2
–3
20
36
68
2
6
VDD
VDD
VDD
UNIT
LSB
LSB
kHz
bits
mV
mA
kΩ
dB
dB
dB
dB
dB
%
V
V
V
V
V
s
9