P10C68- ZARLINK [Zarlink Semiconductor Inc], P10C68- Datasheet - Page 13

• Manufacturer Part Number: P10C68-
• Description: CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

OPERATING NOTES
to P10C68 only and can be ignored for P11C68.
mode and non-volatile mode. In SRAM mode, the memory
operates as an ordinary static RAM. While in non-volatile
mode, data is transferred in parallel from SRAM to EEPROM
or from EEPROM to SRAM.
SRAM READ
(bar) are LOW and NE (bar) and W (bar) are HIGH. The
address specified by the thirteen address pins A
which of the 8192 data bytes will be accessed. When the
READ is initiated by an address transistion, the outputs will be
valid after a delay of t
ADDRESS
ADDRESS
Note: References to NE (bar) should be taken as applying
The devices have two separate modes of operation: SRAM
The devices perform a read cycle when ever E (bar) and G
(DATA
(DATA
OUT)
OUT)
DQ
DQ
E
INVALID
AVQV
t
SKEW
t
AVEL
(READ CYCLE 1).
ADDRESS 1
DATA VALID
t
t
AVAV
ELEH
ADDRESS 1
t
AVAV
DATA VALID
t
EHAX
ADDRESS 2
0-12
t
determine
AVAV
DATA
be valid at t
The data outputs will repeatedly respond to address changes
within the t
any control input pins and will remain valid until another
address change or until E (bar) or G (bar) is brought HIGH or
W (bar) or NE (bar) is brought LOW.
SRAM WRITE
are LOW and NE (bar) is HIGH. The address inputs must be
stable prior to entering the WRITE cycle and must remain
stable until either E (bar) or W (bar) go HIGH at the end of the
cycle. The data on the eight pins DQ
memory location specified by the address inputs if valid t
before the end of a W (bar) controlled WRITE or t
the end of an E (bar) controlled WRITE.
VALID
If the READ is initiated by E (bar) or G (bar), the outputs will
A write cycle is performed whenever E (bar) and W (bar)
ADDRESS 6
t
AVAV
DATA VALID
ADDRESS 6
AVQV
t
ELQV
ELQZ
t
AVAV
access time without the need for transitions on
or t
DATA VALID
t
t
STORE /
AVQZ
GLQV
t
STORE /
, whichever is later. (READ CYCLE 2).
IMPEDANCE
t
RECALL
HIGH
t
RECALL
IMPEDANCE
HIGH
0-7
, will be written into the
P10C68/P11C68
DATA VALID
DATA VALID
DVEH
before
DVWH
13