CMX624P4 CMLMICRO [CML Microcircuits], CMX624P4 Datasheet - Page 14

• Manufacturer Part Number: CMX624P4
• Description: V.23 / Bell 202 Modem
• Manufacturer: CMLMICRO [CML Microcircuits]

V23 / Bell 202 Modem
1.5.12 ‘C-BUS’ Registers
Write Only ‘C-BUS’ Registers
Read Only ‘C-BUS’ Registers
Notes:
 2003 CML Microsystems Plc
Addr
Addr
$EE
$EA
$E0
$E1
$E3
$E7
$EF
$01
1.
2.
3.
4.
5.
6.
TONES
RESET
SETUP
FLAGS
MODE
MASK
DATA
DATA
Reg.
Reg.
FSK
** See notes 2 and 3
IRQ
RX
TX
TX
Accessing the RESET Register over the ‘C-BUS’ clears all of the bits in the SETUP, TX TONES,
TX DATA, FSK MODE and IRQ MASK registers, and bits 0-3 and 5 of the FLAGS Register to
‘0’. This will set the device into Zero Power mode. Note that this is a single-byte ‘C-BUS’
transaction consisting solely of the address byte value $01.
Note that putting the device in Zero Power mode by directly setting SETUP Bit 4 to ‘0’ does not
clear the other register bits. Care should be taken before re-enabling the device that the other
bits are set so as to prevent undesired transient operation. In particular, bit 6 of the TXTONES
Register should be set to ‘0’ to prevent modulation of the transmitter output.
If any of bits 0, 1, 2, 3 or 5 of the FLAGS Register is ‘1’ and the corresponding bit of the IRQ
MASK Register is also ‘1’ then the IRQN output of the CMX624 will be pulled low.
Bit 5 (Ring Detect Change) of the FLAGS Register is set on every ‘0’ to ‘1’ or ‘1’ to ‘0’ change of
bit 6 (Ring Detect).
Clearing bit 4 of the SETUP Register puts the CMX624 into the Zero Power mode by turning off
all blocks except for the ‘C-BUS’ interface and Ring Detector circuit.
Reading the FLAGS Register clears the IRQN output and also clears bits 0, 1, 2, 3 and 5 of the
FLAGS Register.
FLAGS Register (bit 4) is ‘1’ whenever the received signal being looked for is detected and ‘0’
when both signals are absent. IRQ MASK Register (bit 4) is normally set to ‘0’ - but can be set
to ‘1’ to enable interrupts on the IRQN output. In the latter case, IRQN will be continuously
pulled to ‘0’ whilst Rx Energy or 2100Hz are present. This may be useful for device evaluation
purposes.
FSK mode:
0 = V.23
1 = Bell 202
Tx Mode:
0 = FSK.
1 = Tones.
D7
0 = Rx Sync
1 = Async
Reserved,
Set to 0
D7
Bad Rx
Parity
N/A
7
7
TXON o/p:
0 = Off
1 = On
Tone or
o/p:
0 = Off.
1 = On.
D6
Rx Equal:
0 = Off
1 = On
Reserved,
Set to 0
D6
Ring Detect
N/A
6
6
FSK
Relay Drive:
0 = o/c
1 = Pull low
Reserved,
set to 0
D5
0 = Rx Call
Progress
1 = Rx FSK
Ring Detect
Change
D5
Ring Detect
Change **
N/A
5
5
Command Data Byte Bits
0 = Zero
Power
1 = Normal
0 = DTMF
1 = Single
tone
D4
0 = Rx 75 /
150 bps
1 = 1200
Reserved,
Set to 0
D4
Rx Energy
or 2100Hz
detect.
Reply Data Byte Bits
14
N/A
4
4
Stop bits:
0 = 1 bit
1 = 2 bits
Reserved,
set to 0
D3
0 = Tx Sync
1 = Async
Rx Data
overflow
D3
Rx Data
overflow **
N/A
3
3
Parity:
0 = None
1 = Parity
Reserved,
set to 0
D2
Tx o/p level:
0 = Normal
1 = +3dB
Rx Data
ready
D2
Rx Data
ready **
N/A
2
2
Parity:
0 = Odd
1 = Even
Reserved,
set to 0
D1
FSK
0 = Off
1 = On
(Tx & Rx)
Tx Data
underflow
D1
Tx Data
underflow **
N/A
enable:
1
1
Data bits:
0 = 8 bits
1 = 7 bits
Set Detect:
0 = FSK/CP
1 = 2100Hz
D0
0 = Tx 75 /
150 bps
1 = 1200 or
DTMF
Tx Data
ready
D0
Tx Data
ready **
CMX624
D/624/7
N/A
0
0