P600-27BSCL PLL [PhaseLink Corporation], P600-27BSCL Datasheet

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P600-27BSCL

Manufacturer Part Number
P600-27BSCL
Description
Ultra Low Current XO 10 MHz to 52 MHz
Manufacturer
PLL [PhaseLink Corporation]
Datasheet
FEATURES
DESCRIPTION
The PLL600-27B form a low cost family of XO IC’s,
designed to consume the lowest current on the mar-
ket for the 10MHz to 52MHz range. It accepts fun-
damental resonant mode crystal input from 10 to
52MHz. Providing less than -145 dBc at 10kHz offset
at 30MHz and with a very low jitter (2.5 ps RMS pe-
riod jitter) makes this chip ideal for applications re-
quiring low current frequency sources.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/03/05 Page 1
XIN/FIN
XOUT
Low phase noise (-145 dBc @ 10kHz offset).
CMOS output with OE tri-state control.
Ultra Low current consumption ( <2mA, at
27MHz, 3.3V)
10 to 52MHz fundamental or 3
12mA drive capability at TTL output.
Low jitter (RMS): 2.5ps period jitter.
1.8V, 2.5V and 3.3V DC operation.
Available in 8 pin SOIC
OSCSEL
XTAL
OSC
OE
rd
OT crystal input.
CLK
Ultra Low Current XO 10 MHz to 52 MHz
PIN ASSIGNMENT (PACKAGE)
PAD LAYOUT
OE LOGIC SELECTION TABLE
OE^
XIN/FIN
1(default)
0
Y
^ : denotes internal pull-up
GND
DNC
Preliminary
OE^
XIN/FIN
X
DNC
G ND
(0,0)
XIN
O E
GND
OE^
1
3
4
1
2
3
4
2
8-pin SOIC
Disabled - osc. off
PLL600-27B
1
2
3
SOT-23
C 500A -0505 -05K
D ie ID:
32 m il
OUTPUT
Enabled
6
5
4
XO U T
8
8
7
6
5
CLK
XOUT
VDD
XOUT
DNC
CLK
7
VDD
(812, 986)
6
5
D NC
VD D
CLK

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P600-27BSCL Summary of contents

Page 1

FEATURES • Low phase noise (-145 dBc @ 10kHz offset). • CMOS output with OE tri-state control. • Ultra Low current consumption ( <2mA, at 27MHz, 3.3V) • 52MHz fundamental or 3 • 12mA drive capability at TTL ...

Page 2

Internal Pull-up, default value is ‘1’ when not connected. PACKAGE PIN DESCRIPTION Pin No. Name SOT-6 SOIC-8 XIN/FIN DNC 3 - GND 4 2 CLK 5 6 VDD 6 5 DNC 7 - XOUT ...

Page 3

AC Electrical Specifications PARAMETERS Input Crystal Frequency Settling time Output Clock Rise/Fall Time VDD sensitivity Output Clock Duty Cycle 3. Jitter and Phase Noise Specifications PARAMETERS RMS Period Jitter (1 sigma – 10,000 samples) Phase Noise relative to carrier ...

Page 4

Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Maximum Sustainable Drive Level Operating Drive Level C0 (for frequencies below 30MHz) C0 (for frequencies above 30MHz) ESR Note: A detailed crystal specification document is also available for this part ...

Page 5

... Note: PhaseLink Supports GREEN Packaging Marking P600-27BSC 8-Pin SOIC (Tube) P600-27BSC 8-Pin SOIC (Tape and Reel) P600-27BSCL 8-Pin SOIC (Tube), GREEN P600-27BSCL 8-Pin SOIC (Tape and Reel), GREEN P600-27BTC 6-Pin SOT (Tape and Reel) PLL600-27B Preliminary NONE= TUBE R= TAPE AND REEL ...

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