74HC/HCT126 Philips Semiconductors (Acquired by NXP), 74HC/HCT126 Datasheet
74HC/HCT126
Related parts for 74HC/HCT126
74HC/HCT126 Summary of contents
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... DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT126 Quad buffer/line driver; 3-state Product specification File under Integrated Circuits, IC06 INTEGRATED CIRCUITS ...
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... CC GENERAL DESCRIPTION The 74HC/HCT126 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The HC/HCT126 are four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A LOW at nOE causes the outputs to assume a HIGH impedance OFF-state. The “ ...
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... December 1990 NAME AND FUNCTION output enable inputs (active HIGH) data inputs data outputs ground (0 V) positive supply voltage Fig.2 Logic symbol. Fig.5 Logic diagram (one buffer). 3 Product specification 74HC/HCT126 (b) (a) Fig.3 IEC logic symbol. FUNCTION TABLE INPUTS OUTPUT nOE ...
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... Product specification 74HC/HCT126 . TEST CONDITIONS UNIT WAVEFORMS +125 (V) min. max. 150 ns 2.0 Fig.6 30 4.5 26 6.0 190 ns 2.0 Fig.7 38 4.5 32 6.0 190 ns 2.0 Fig.7 38 4 ...
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... amb 74HCT + +85 min. typ. max. min. max Product specification 74HC/HCT126 . TEST CONDITIONS UNIT WAVEFORMS +125 (V) min. max 4.5 Fig 4.5 Fig 4.5 Fig 4.5 Fig.6 ...
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... Fig.6 Waveforms showing the input (nA) to output (nY) propagation delays and the output transition times GND HCT 1 GND Fig.7 Waveforms showing the 3-state enable and disable times. PACKAGE OUTLINES “74HC/HCT/HCU/HCMOS Logic Package Outlines” See December 1990 . 6 Product specification 74HC/HCT126 ...