74HC/HCT191 Philips Semiconductors (Acquired by NXP), 74HC/HCT191 Datasheet
74HC/HCT191
Related parts for 74HC/HCT191
74HC/HCT191 Summary of contents
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... DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT191 Presettable synchronous 4-bit binary up/down counter Product specification File under Integrated Circuits, IC06 ...
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... Output capability: standard I category: MSI CC GENERAL DESCRIPTION The 74HC/HCT191 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT191 are asynchronously presettable 4-bit binary up/down counters. They contain four master/slave ...
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... For HCT the condition GND ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information” December 1990 pF notes 1 and where 1 Product specification 74HC/HCT191 TYPICAL CONDITIONS HC HCT = 3.5 3 UNIT ns MHz pF pF ...
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... LOW) up/down input ground (0 V) parallel load input (active LOW) terminal count output ripple clock output (active LOW) clock input (LOW-to-HIGH, edge triggered) data inputs positive supply voltage Fig.2 Logic symbol. 4 Product specification 74HC/HCT191 Fig.3 IEC logic symbol. ...
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... TERMINAL COUNT STATE Product specification 74HC/HCT191 OUTPUTS count up X count down X no change OUTPUTS ...
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... Philips Semiconductors Presettable synchronous 4-bit binary up/down counter Fig.6 Synchronous n-stage counter using ripple carry/borrow. Fig.7 Synchronous n-stage counter with parallel gated carry/borrow. December 1990 Fig.5 N-stage ripple counter using ripple clock. 6 Product specification 74HC/HCT191 ...
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... Presettable synchronous 4-bit binary up/down counter Sequence Load (preset) to binary thirteen; count up to fourteen, fifteen, zero, one and two; inhibit; count down to one, zero, fifteen, fourteen and thirteen. Fig.8 Typical load, count and inhibit sequence. December 1990 Fig.9 Logic diagram. 7 Product specification 74HC/HCT191 ...
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... Product specification 74HC/HCT191 . TEST CONDITIONS UNIT WAVEFORMS 125 (V) 330 ns 2.0 Fig.10 66 4.5 56 6.0 395 ns 2.0 Fig.10 77 4.5 65 6.0 225 ns 2.0 Fig.11 45 4.5 38 6.0 195 ns 2.0 Fig. ...
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... Product specification 74HC/HCT191 TEST CONDITIONS UNIT WAVEFORMS 125 ( 2.0 Fig.15 11 4.5 9 6.0 310 ns 2.0 Fig.17 62 4.5 53 6.0 150 ns 2.0 Fig.16 30 4.5 26 6.0 210 ns 2.0 Fig. ...
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... The value of additional quiescent supply current ( I To determine I per input, multiply this value by the unit load coefficient shown in the table below. CC INPUT UNIT LOAD COEFFICIENT D 0 0.65 U/D 1.15 CE, PL 1.5 December 1990 ) for a unit load given in the family specifications Product specification 74HC/HCT191 . ...
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... Product specification 74HC/HCT191 TEST CONDITIONS UNIT WAVEFORMS 125 ( 4.5 Fig. 4.5 Fig. 4.5 Fig. 4.5 Fig. 4.5 Fig. 4.5 Fig. 4.5 Fig ...
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... Fig.11 Waveforms showing the clock and count enable inputs (CP, CE) to ripple clock output (RC) propagation delays GND HCT : GND Fig.12 Waveforms showing the input (D December 1990 ) propagation delays, the clock pulse width and the output (Q ) propagation delays Product specification 74HC/HCT191 ...
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... Fig.14 Waveforms showing the up/down count input (U/D) to terminal count and ripple clock output (TC, RC) propagation delays GND HCT : GND Fig.15 Waveforms showing the parallel load input (PL) pulse width, removal time to clock (CP) and the output (Q ) transition times. n December 1990 ) propagation delays Product specification 74HC/HCT191 ...
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... V = GND HCT : GND Fig.17 Waveforms showing the set-up and hold times from the count enable and up/down inputs (CE, U/D) to the clock (CP). PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines” December 1990 . 14 Product specification 74HC/HCT191 ). n ...