74HC/HCT192 Philips Semiconductors (Acquired by NXP), 74HC/HCT192 Datasheet - Page 2

• Manufacturer Part Number: 74HC/HCT192
• Description: Presettable Synchronous BCD Decade Up/down Counter
• Manufacturer: Philips Semiconductors (Acquired by NXP)

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT192 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT192 are synchronous BCD up/down
counters. Separate up/down clocks, CP
respectively, simplify operation. The outputs change state
synchronously with the LOW-to-HIGH transition of either
clock input. If the CP
HIGH, the device will count up. If the CP
while CP
one clock input can be held HIGH at any time, or
erroneous operation will result. The device can be cleared
at any time by the asynchronous master reset input (MR);
it may also be loaded in parallel by activating the
asynchronous parallel load input (PL).
The “192” contains four master-slave JK flip-flops with the
necessary steering logic to provide the asynchronous
reset, load, and synchronous count up and count down
functions.
Each flip-flop contains JK feedback from slave to master,
such that a LOW-to-HIGH transition on the CP
decrease the count by one, while a similar transition on the
CP
December 1990
Synchronous reversible counting
Asynchronous parallel load
Asynchronous reset
Expandable without external logic
Output capability: standard
I
Presettable synchronous BCD decade
up/down counter
CC
U
input will advance the count by one.
category: MSI
U
is held HIGH, the device will count down. Only
U
clock is pulsed while CP
U
D
and CP
clock is pulsed
D
D
input will
is held
D
2
One clock should be held HIGH while counting with the
other, otherwise the circuit will either count by two’s or not
at all, depending on the state of the first flip-flop, which
cannot toggle as long as either clock input is LOW.
Applications requiring reversible operation must make the
reversing decision while the activating clock is HIGH to
avoid erroneous counts.
The terminal count up (TC
(TC
reached the maximum count state of 9, the next
HIGH-to-LOW transition of CP
TC
the count up clock.
Likewise, the TC
the zero state and the CP
outputs can be used as the clock input signals to the next
higher order circuit in a multistage counter, since they
duplicate the clock waveforms. Multistage counters will not
be fully synchronous, since there is a slight delay time
difference added for each stage that is added.
The counter may be preset by the asynchronous parallel
load capability of the circuit. Information present on the
parallel data inputs (D
and appears on the outputs (Q
conditions of the clock inputs when the parallel load (PL)
input is LOW. A HIGH level on the master reset (MR) input
will disable the parallel load gates, override both clock
inputs and set all outputs (Q
clock inputs is LOW during and after a reset or load
operation, the next LOW-to-HIGH transition of that clock
will be interpreted as a legitimate signal and will be
counted.
U
D
will stay LOW until CP
) outputs are normally HIGH. When the circuit has
D
output will go LOW when the circuit is in
0
to D
D
U
U
goes LOW. The terminal count
) and terminal count down
3
goes HIGH again, duplicating
0
) is loaded into the counter
U
to Q
0
will cause TC
to Q
74HC/HCT192
3
Product specification
) LOW. If one of the
3
) regardless of the
U
to go LOW.