74HC/HCT194 Philips Semiconductors (Acquired by NXP), 74HC/HCT194 Datasheet - Page 2

• Manufacturer Part Number: 74HC/HCT194
• Description: 4-bit Bidirectional Universal Shift Register
• Manufacturer: Philips Semiconductors (Acquired by NXP)

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT194 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The functional characteristics of the 74HC/HCT194 4-bit
bidirectional universal shift registers are indicated in the
logic diagram and function table. The registers are fully
synchronous.
The “194” design has special features which increase the
range of application. The synchronous operation of the
device is determined by the mode select inputs (S
As shown in the mode select table, data can be entered
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
December 1990
SYMBOL
t
t
f
C
C
PHL
PHL
max
Shift-left and shift-right capability
Synchronous parallel and serial data transfer
Easily expanded for both serial and parallel operation
Asynchronous master reset
Hold (“do nothing”) mode
Output capability: standard
I
4-bit bidirectional universal shift register
I
PD
CC
f
f
C
V
i
o
/ t
CC
PD
= input frequency in MHz
L
category: MSI
= output frequency in MHz
= (C
PLH
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
D
L
= C
amb
V
PD
PARAMETER
propagation delay
maximum clock frequency
input capacitance
power dissipation capacitance per package
CC
MR to Q
CP to Q
= 25 C; t
2
V
CC
f
o
) = sum of outputs
2
n
n
f
r
i
= t
I
= GND to V
f
= 6 ns
(C
L
V
CC
2
CC
; for HCT the condition is V
f
o
) where:
0
, S
1
).
2
and shifted from left to right (Q
to left (Q
entered, loading all 4 bits of the register simultaneously.
When both S
a hold (“do nothing”) mode. The first and last stages
provide D-type serial data inputs (D
multistage shift right or shift left data transfers without
interfering with parallel load operation.
Mode select and data inputs are edge-triggered,
responding only to the LOW-to-HIGH transition of the
clock (CP). Therefore, the only timing restriction is that the
mode control and selected data inputs must be stable one
set-up time prior to the positive transition of the clock
pulse.
The four parallel data inputs (D
Data appearing on the D
HIGH, is transferred to the Q
following the next LOW-to-HIGH transition of the clock.
When LOW, the asynchronous master reset (MR)
overrides all other input conditions and forces the Q
outputs LOW.
The “194” is similar in operation to the “195” universal shift
register, with added features of shift-left without external
connections and hold (“do nothing”) modes of operation.
D
CONDITIONS
C
notes 1 and 2
in W):
L
= 15 pF; V
3
I
= GND to V
0
Q
and S
2
CC
= 5 V
Q
1
1
are LOW, existing data is retained in
, etc.) or parallel data can be
CC
0
to D
14
11
102
3.5
40
1.5 V
0
HC
3
0
to Q
inputs, when S
0
TYPICAL
to D
74HC/HCT194
Product specification
3
Q
SR
outputs respectively,
1
3
15
15
77
3.5
40
) are D-type inputs.
, D
HCT
SL
Q
2
) to allow
, etc.) or, right
0
and S
ns
ns
MHz
pF
pF
UNIT
1
are