S3031BH0 AMCC [Applied Micro Circuits Corporation], S3031BH0 Datasheet

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S3031BH0

Manufacturer Part Number
S3031BH0
Description
E4/STM-1/OC-3 ATM TRANSCEIVER
Manufacturer
AMCC [Applied Micro Circuits Corporation]
Datasheet
FEATURES
APPLICATIONS
Figure 1a. Electrical Interface
Figure 1b. Optical Interface
DEVICE
SPECIFICATION
August 19, 1999 / Revision D
E4/STM-1/OC-3 ATM TRANSCEIVER
E4/STM-1/OC-3 ATM TRANSCEIVER
Complies with Bellcore and ITU-T
specifications
On-chip high-frequency PLLs for clock
generation and clock recovery
On-chip analog circuitry for transformer
driver and equalization
Supports 139.264 Mbps (E4) and 155.52
Mbps (OC-3) transmission rates
Supports 139.264 Mbps and 155.52 Mbps
Coded Mark Inversion (CMI) interfaces
TTL Reference frequencies of 19.44 and
38.88 MHz (OC-3) or 17.408 and 34.816
MHz (E4)
Interface to both PECL and TTL logic
Lock detect on clock recovery function —
monitors run length and frequency
Serial and 4 bit (nibble) system interfaces
Low jitter PECL interface
+5V operation
100 PQFP/TEP package
Supports both electrical and optical interfaces
ATM over SONET/SDH
OC-3/STM-1 or E4-based transmission
systems
OC-3/STM-1 or E4 modules
OC-3/STM-1 or E4 test equipment
Section repeaters
Add Drop Multiplexers (ADM)
Broadband cross-connects
Fiber optic terminators
Fiber optic test equipment
E4/STM-1/OC-3
E4/STM-1/OC-3
PROCESSOR
PROCESSOR
OVERHEAD
OVERHEAD
OSC
OSC
139.264/155.52 Mbps NRZ
139.264/155.52 Mbps NRZ
139.264/155.52 Mbps NRZ
139.264/155.52 Mbps NRZ
17.408/19.44 MHz
17.408/19.44 MHz
GENERAL DESCRIPTION
The S3031B transceiver chip is a fully integrated CMI
encoding transmitter and CMI decoding receiver. The
chip derives high speed timing and data signals for
SONET/SDH or PDH-based equipment. The circuit is
implemented using AMCC’s proven Phase Locked Loop
(PLL) technology. Figures 1a and 1b show typical
network applications.
The S3031B has two independent VCOs which are
synchronized to the local NRZ transmitted data and the
received CMI data respectively. The chip can be used
with either a 19.44 MHz or a 38.88 MHz reference clock
when operated in the SONET/SDH OC-3 mode. In E4
mode the chip can be operated with a 17.408 MHz or a
34.816 MHz reference in support of existing system
clocking schemes. On-chip coded-mark-inversion (CMI)
encoding and decoding is provided for 139.264 Mbps
and 155.52 Mbps interfaces.
The low jitter PECL interface for the serial data inputs
and the PECL nibble clock interface guarantee com-
pliance with the bit-error rate requirements of the Bellcore
and ITU-T standards. The S3031B is packaged in a
0.65 mm pitch 100-pin PQFP/TEP.
The S3031B provides the major active components on-
chip for a coaxial cable interface, including analog
transformer driver circuitry and equalization interface
circuitry. Discrete controls permit separate selection of
CMI or NRZ operation and analog (coaxial copper) or
PECL (optical module) media interfaces. Both line
loopback and diagnostic local loopback operation are
supported.
S3031B
S3031B
XCVR
XCVR
139.264/155.52 Mbps
139.264/155.52 Mbps
139.264/155.52 Mbps CMI
139.264/155.52 Mbps CMI
OTX
ORX
XFMR
XFMR
COAX
COAX
S3031B
S3031B
®
1

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S3031BH0 Summary of contents

Page 1

DEVICE E4/STM-1/OC-3 ATM TRANSCEIVER SPECIFICATION E4/STM-1/OC-3 ATM TRANSCEIVER FEATURES • Complies with Bellcore and ITU-T specifications • On-chip high-frequency PLLs for clock generation and clock recovery • On-chip analog circuitry for transformer driver and equalization • Supports 139.264 Mbps (E4) ...

Page 2

S3031B SONET/SDH OVERVIEW Synchronous Optical Network (SONET standard for connecting one fiber system to another at the op- tical level. SONET, together with the Synchronous Digital Hierarchy (SDH) administered by the ITU-T, form a single international standard for ...

Page 3

E4/STM-1/OC-3 ATM TRANSCEIVER S3031B OVERVIEW The S3031B transceiver can be used to implement the front end of STS-3, OC equipment. The block diagram in Figure 9 shows the basic operation of the chip. When the S3031B is operating ...

Page 4

S3031B Parallel-to-Serial Converter The parallel-to-serial converter shown in Figure 9 is comprised of two 4-bit registers. The first register latches the data from the PIN[3:0] bus on the rising edge of REFCLK. The second register is a parallel loadable shift ...

Page 5

E4/STM-1/OC-3 ATM TRANSCEIVER Figure 7. Mask of a pulse corresponding to a binary 0 Compliant to G.703 Figure 8. Mask of a pulse corresponding to a binary 1 Compliant to G.703 Notes: 1. The maximum “steady state” amplitude should not ...

Page 6

S3031B Figure 9. S3031B OC-3/STM-1/E4 Transceiver CAP1 LOOP FILTER CAP2 REFCLK TSTCLKEN REFSEL CMISEL TXRSTB DLCV 4:1 PARALLEL 4 TO SERIAL PIN[3:0] 2:1 TSDATIP/N MUX 2 XFRMENA/B SERDATEN CAP3 CAP4 SERDSEL TSTCLKEN TESTCLK CMISEL RXRSTB GIN G GOUT 2 BUFINA, ...

Page 7

E4/STM-1/OC-3 ATM TRANSCEIVER S3031B RECEIVER OPERATION The S3031B transceiver chip provides the first stage of the digital process of a receive SONET STS-3 or ITU serial bit stream. A Coded Mark Inversion (CMI) decoder can be enabled for ...

Page 8

S3031B In NRZ mode, a logic Low level on the LOSOPT input will cause the PLL to change its reference to the reference clock. This pin should be driven by a PECL compatible level signal detect signal from the fiber ...

Page 9

E4/STM-1/OC-3 ATM TRANSCEIVER Table 2. Transmitter Input Pin Assignment and Description ...

Page 10

S3031B Table 3. Transmitter Output Pin Assignment and Description ...

Page 11

E4/STM-1/OC-3 ATM TRANSCEIVER Table 4. Receiver Input Pin Assignment and Description ...

Page 12

S3031B Table 4. Receiver Input Pin Assignment and Description (Continued ...

Page 13

E4/STM-1/OC-3 ATM TRANSCEIVER Table 5. Receiver Output Pin Assignment and Description ...

Page 14

S3031B Table 6. Common Pin Assignment and Description ...

Page 15

E4/STM-1/OC-3 ATM TRANSCEIVER Table 6. Common Pin Assignment and Description (Continued ...

Page 16

S3031B Figure 13. 100-Pin PQFP/TEP Package TOP VIEW Thermal Management Device S3031 1. Max ambient temperature permitted in still air to maintain Tj < 130˚C. 16 E4/STM-1/OC-3 ATM TRANSCEIVER ja Still Air Power w/DW0045-28 1.92W 19˚C/W SIDE VIEW 1 Max ...

Page 17

E4/STM-1/OC-3 ATM TRANSCEIVER Figure 14. Heat Sink Drawing DW0045-28 August 19, 1999 / Revision D S3031B 17 ...

Page 18

S3031B Figure 15. S3031B Pinout PIN3 TXINVEE TXINVCC TXCRVCC TXCRVEE REFCLK REFGND SERDATEN TSCLKOP TSCLKON TSVCC TSDATOP TSDATON TSVEE TSDATIP TSDATIN GND AVCC1 AVEE1 CGND CAP1 CAP2 CGND AVEE0 AVCC0 TSTCLKEN CMISEL TESTCLK AVCC4 BUFINA 18 E4/STM-1/OC-3 ATM TRANSCEIVER 1 ...

Page 19

E4/STM-1/OC-3 ATM TRANSCEIVER Table 7. S3031B Clock Recovery Mode Performance Specifications ...

Page 20

S3031B Table 10. Electrical Characteristics for ANDATIN Input (V = +5V +25 C, input AC coupled unless otherwise noted ...

Page 21

E4/STM-1/OC-3 ATM TRANSCEIVER Table 13. Electrical Characteristics for BUFIN, BUFOUT ( +5VDC coupled and T CC LOAD ...

Page 22

S3031B Table 16. TTL Input/Output DC Characteristics ( ...

Page 23

E4/STM-1/OC-3 ATM TRANSCEIVER Figure 16. Differential ECL Input Application Fiber Optic Receiver Figure 17. S3031B Differential ECL Output Application Figure 18. Loop Filter Capacitor Connections 1.0 F Note 100 for serial mode, and R = 1000 for nibble ...

Page 24

S3031B Figure 19. S3031B Transformer Input and Output Application 0. 0. 12pF RX INPUT E4/STM-1/OC-3 ATM TRANSCEIVER CABLE OUT 220 C1 0.01 F 0.01 F 100 300 24pF MMBD352 ...

Page 25

E4/STM-1/OC-3 ATM TRANSCEIVER Figure 20. OC-3 Application TX_CLK_+/– SUNI IGT SYN155 RX_CLK_+/– RX_DATA_+/– TX_DATA_+/– Figure 21. STM-1 CMI, E4 Application REFCKIN TX_DATA_+/– SUNI-LITE SUNI-PLUS SABRE RX_CLK_+/– RX_DATA_+/– August 19, 1999 / Revision D 19.44 MHz 155.52 MHZ TSCLKOP/N S3031B REFCLK ...

Page 26

S3031B Table 18. Suggested Interface Devices Processor Interface PMC PM5345 PMC PM5346 PMC PM5347 IGT WAC-013-A TRANSWITCH SYN155 TI SABRE TDC 1500 Electrical Interface Motorola Mini-Circuits Mini-Circuits Optical Interface HP HFBR-520x CTS ODL-1408X Sumitomo SDM4123-XC AMP 269039-1 Ordering Information GRADE ...

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