16C6N4 RENESAS [Renesas Technology Corp], 16C6N4 Datasheet - Page 66
16C6N4
Manufacturer Part Number
16C6N4
Description
Renesas MCU
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.16C6N4.pdf
(92 pages)
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M16C/6N Group (M16C/6N4)
Rev.2.40
REJ03B0003-0240
Under development
This document is under development and its contents are subject to change.
Figure 5.14 Timing Diagram (2)
Memory Expansion Mode and Microprocessor Mode
(Effective for setting with wait)
(Common to setting with wait and setting without wait)
BCLK
HLDA output
BCLK
RD
(Separate bus)
RD
(Multiplexed bus)
RDY input
HOLD input
P0, P1, P2,
P3, P4,
P5_0 to P5_2
(Separate bus)
WR, WRL, WRH
WR, WRL, WRH
(Multiplexed bus)
Measuring conditions :
NOTE:
VCC = 5 V
Input timing voltage : Determined with V
Output timing voltage: Determined with V
Aug 25, 2006
1. The above pins are set to high-impedance regardless of the input level of the BYTE pin,
the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register.
(1)
page 66 of 88
t
su(HOLD–BCLK)
t
d(BCLK–HLDA)
tsu(RDY–BCLK)
t
h(BCLK–HOLD)
IL
OL
Hi–Z
= 1.0 V, V
= 2.5 V, V
t
d(BCLK–HLDA)
IH
OH
= 4.0 V
= 2.5 V
5. Electric Characteristics (Normal-ver.)
th(BCLK–RDY)
VCC = 5 V
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