BR24G32-3A ROHM [Rohm], BR24G32-3A Datasheet - Page 17

• Manufacturer Part Number: BR24G32-3A
• Description: High Reliability Serial EEPROMs I2C BUS BR24xxxxfamily
• Manufacturer: ROHM [Rohm]

●Read Command
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© 2012 ROHM Co., Ltd. All rights reserved.
BR24G32-3A
TSZ22111・15・001
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μ-COM) side, the next address
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
SDA
LINE
○Read cycle
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input
'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
data can be read in succession.
'H' .
signal 'H'.
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can
be read in succession.
S D A
L IN E
SDA
LINE
A
R
S
T
T
1 0
ADDRESS
S
T
A
R
T
S
T
A
R
T
SLAVE
1
1 0
1 0
0
A2
A D D R E S S
ADDRESS
A1
S LA V E
SLAVE
1
Fig.40 Sequential read cycle (in the case of current read cycle)
1
Fig.39 Current read cycle
A0
0
W
0
R
/
W
R
T
E
I
A2
A 2
A
C
K
A1
WA
15
A 1
A0
WA
ADDRESS（ｎ）
14
A 0
1st WORD
WA
13
W
R
E
A
D
R
/
W
WA
R
E
A
D
R
12
*1
/
A
C
K
WA
11
A
C
K
D7
D 7
Fig.38 Random read cycle
DATA(n)
A
C
K
D A TA (n )
ADDRESS（ｎ）
2nd WORD
D0
A
C
K
D 0
WA
C
A
K
0
A
C
K
S
O
P
T
S
T
A
R
T
1 0
ADDRESS
SLAVE
1
0
A2 A1
A
C
K
17/34
A0
D7
R
W
/
R
E
A
D
A
C
K
DATA(n+x)
D7
DATA(n)
D0
D0
A
C
K
S
T
O
P
A
C
K
O
S
T
P
*1 WA12 to WA15 become don’t care.
TSZ02201-0R2R0G100050 -1-2
15.May.2012 REV.001
Datasheet
Datasheet