TSS463-AAR ATMEL [ATMEL Corporation], TSS463-AAR Datasheet
TSS463-AAR
Related parts for TSS463-AAR
TSS463-AAR Summary of contents
Page 1
... TSS463AA. Messages are encoded in enhanced Manchester code, and an optional pulsed code for use with an optical or radio link maximum bit rate of 1 Mbit/s. The TSS463AA analyzes the messages received or transmitted according to 6 different criteria includ- ing some higher level checks. ...
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... Block Diagram TSS463-AA 2 4205B–AUTO–12/04 ...
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... XTAL2 6 TEST/VSS 7 CKOUT 8 RXD1 9 RXD2 10 RXD0 11 TXD 12 GND 13 RESET 14 SCLK 15 MOSI 16 TSS463-AA TOP VIEW 16 MOSI 15 SCLK 14 RESET 13 GND 12 TXD 11 RXD0 10 RXD2 RXD1 9 Pin Function SPI/SCI Data Output SPI/SCI Slave Select (active low) Interrupt (active low power supply Crystal oscillator or clock input pin from MHz ...
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... CKOUT 8 Notes: 1. The TSS463AA RESET pin can either be connected to GND through a 1 µF capaci- tor, or the µC RESET pin or unconnected (inactive with internal pull-up). 2. Leaving MISO output pin floating in high impedance mode slightly increases standby consumption. A 100 K pull-up/pull-down resistor is recommended. ...
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... The processor controls the TSS463AA by reading and writing the internal registers of the circuit. These registers appear to the processor as regular memory locations. The TSS463AA must be connected with an SPI or SCI serial interface. The following section provides information on switching from one mode to another. The first two bytes to be sent by the master (CPU) are called “Initialization Sequence”: This sequence provides a proper asynchronous RESET in the TSS463AA and it selects the Motorola SPI, Intel SPI or the SCI serial mode ...
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... The SS pin is the slave chip select low active. A low state on the Slave Select input allows the TSS463AA to accept data on the MOSI pin and send data on the MISO pin. The Slave Select signal must not toggle between each transmitted byte and should be left at a low level during the whole SPI frame ...
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... Address, Address + 1, Address + 2,..., Address + n with 28). To make sure the TSS463AA is not out of synchronization, the SPI interface will trans- mit data “0xAA" and "0x55” on the MISO pin during address and control byte time. This way, the master always ensures the TSS463AA is well-synchronized ...
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... When the master (CPU) conducts a read, it sends an address byte, a control byte and dummy characters ("0xFF" for instance) on its MOSI line. In the case of a VAN mes- sages RAM read (VAN frame received), the first data byte sent back by the TSS463AA on its MISO pin is the data length so the master knows how many dummy characters it must send to read the VAN frame properly ...
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... It is the only excep- tion in this mode compared with the Motorola SPI mode. The SCI mode is the third type of interface. The TSS463AA enters this mode if the Ini- tialization Sequence contains (first two bytes received) "0x00, 0xFF". ...
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... not asserted, MISO pin is in high impedance state and incoming data is not driven to the serial data register. Same as the SPI protocol described earlier except for data arranging (LSB first and MSB last). Only 8 bits are monitored by the TSS463AA and master must monitor the 8 first th bits too (9 bit always equal to 1). ...
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... The different blocks of the TSS463AA need to be turned on synchronously. The release of the internal reset is synchronous and a loose of clock can let the TSS463AA in per- manent reset after applying Reset important to note that even after a reset on the RESET pin, the user should wait for 12 clock periods before sending the " ...
Page 12
... XTAL Min 0xFF An oscillator is integrated in the TSS463AA, and consists of an inverting amplifier of which the input is XTAL1 and the output XTAL2. A parallel resonance quartz crystal or ceramic resonator must be connected to these pins. As shown in Figure 5, two capacitors have to be connected from the crystal pins to ground ...
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... TSS463-AA 4 MHz 2 MHz KTS/s Kbits/s KTS/s 250 200 125 125 100 62.50 62.50 50 31.25 31.25 25 15.625 15.625 12.5 7.813 7.813 6.25 3.906 3.906 3.125 1.953 1 ...
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... The data on the line is encoded according to the VAN standard ISO/11519-3. This means that the TSS463AA is using a two level signal having a recessive (1) and a dom- inant (0) state. Furthermore, due to the simple medium used, all data transmitted on the bus is also received simultaneously. ...
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... Slave DATA Figure 12 shows a normal VAN bus frame initiated with a Start of Frame (SOF) sequence shown in Figure 14. The SOF can only be transmitted by an autonomous module. During the preamble, the TSS463AA will synchronize its bit rate clock to the data received. TSS463-AA Frame ...
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... PRESCALED CLOCKS 0 The IFS is defined minimum of 64 prescaled clock periods. The TSS463AA, accepts an IFS of zero prescaled clocks for the reception only of a SOF sequence. Once the bus has been determined as being free, the module must autono- mous module, emit an SOF sequence or synchronous access module, wait until it detects a preamble sequence ...
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... In order to conform with the standard, a received frame includes the combination R/W. RTR = 01 is ignored without any IT generation. All the bits in the command field are automatically handled by the TSS463AA, so the user need not to be concerned for encoding and decoding of these bits. The command bits transmitted on the VAN bus are calculated from the current status of the active message ...
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... However, since the CRC is calculated automatically from the identifier, command and data fields by the TSS463AA, therefore, the user should not be concerned with the cir- cuit. When the frame check sequence has been transmitted, the transmitting module must transmit an End of Data (EOD) sequence, followed by the ACKnowledge field (ACK) and the End of Frame sequence (EOF) to terminate the transfer ...
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... Dominant for no acknowledge from Transmitter R/W : Dominant from Transmitter RTR : Dominant from Transmitter - (*) Manchester bit ACK : Absent from Transmitter and from Receiver because RAK is Dominant 4205B–AUTO–12/04 IDENTIFIER DATA IDENTIFIER DATA IDENTIFIER DATA IDENTIFIER DATA TSS463-AA CRC EOF CRC EOF CRC EOF CRC EOF 19 ...
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... Bus EXT : Recessive from Requestor RAK : Recessive for acknowledge from Requestor R/W : Recessive from Requestor RTR : Recessive from Requestor - (*) Manchester bit ACK : Absent from Requestor and Positive from Requestee because RAK is Recessive TSS463-AA 20 IDENTIFIER DATA IDENTIFIER DATA IDENTIFIER IDENTIFIER CRC CRC CRC ...
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... Recessive from Replyer RAK : Recessive for acknowledge from Replyer R/W : Recessive from Replyer RTR : Dominant from Replyer ACK : Absent from Replyer and Positive from Receiver because RAK is Recessive 4205B–AUTO–12/04 IDENTIFIER DATA IDENTIFIER DATA - (*) Manchester bit TSS463-AA CRC EOF CRC EOF 21 ...
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... Diagnosis System Diagnosis States TSS463-AA 22 The purpose of the diagnosis system is to detect any short or open circuits on either the DATA or DATA lines and to permit possible, to carry the communications on the non-defective line. The diagnosis system is based on the assumption that three separate line receivers are connected to the VAN bus see Figure 1: • ...
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... Synchronous diagnosis The synchronous diagnosis counts the number of edges on the data input connected to the reception logic during one SDC period. If there are less than four edges during one SDC period, the diagnosis mode will change to the major error mode. TSS463- timeslot). 23 ...
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... Signals RI Signal (Return to Idle) SDC Signal (Synchronous Diagnosis Clock) TIP Signal (Transmission in Progress) TSS463-AA 24 • Transmission diagnosis The transmission compares RxD1 and RxD2 inputs (through the input comparators and the filters) with the data transmitted on TxD output time when the transmission logic generates a dominant - recessive transition, the inputs can give different values ...
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... Four programming modes determine how to use the three different inputs and the diag- nosis system. • 3 specified selection modes • 1 automatic selection mode Table 4. Programming Modes Ma Mb Operating Mode 0 0 Differential communication 0 1 Degraded communication on RxD2 (DATA Degraded communication on RxD1 (DATA Automatic selection according the diagnosis status TSS463-AA 25 ...
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... Value after RESET is found after register name value is given, the register is not initialized at RESET. TSS463-AA 26 The TSS463AA memory map consists of three different areas, the Control and Status registers, the Channel registers and the Message data (or Mailbox). Channel 13 Channel 13 ...
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... The user can invert the logical levels used on either the TxD output or the RxD inputs in order to adapt to different line drivers and receivers. One: A one on either of these bits will invert the respective signals. Zero: (Default at reset). The TSS463AA will set TxD to recessive state in Idle mode and consider the bus free (recessive states on RxD inputs). 7 ...
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... The three different module types are supported (see “VAN Frame” on page 15): One: The TSS463AA is at once an autonomous module (Rank 0), a synchronous access module (Rank slave module (Rank 16). Zero: The TSS463AA is at once an synchronous access module (Rank slave module (Rank 16). Max transmissions ...
Page 29
... For each module, determine the largest interframe spacing, LIFS (*). 2. For the whole network, get the maximum LIFS, MAX-LIFS. 3. SDC period > MAX-LIFS. (*) IFS min Example: For VAN frame speed rate = 62,5 KTS µs), SDC >100 ms => 100 µs = 6250, divider chosen: 8192, SDC [3:0] = 0111. TSS463- SDC0 Ma ...
Page 30
... Section “Sleep Command”, page 52).If the user sets the Sleep bit, the circuit will enter sleep mode. When the circuit is in sleep mode, all non-user registers are setup to minimize power consumption. Read/write accesses to the TSS463AA via the SPI/SCI interface are impossible, the oscillator is stopped. ...
Page 31
... Section “Idle and Activate Commands”, page 52). If the user sets the Idle bit, the circuit will enter idle mode. In idle mode the oscillator will operate, but the TSS463AA will not transmit or receive anything on the bus, and the TxD output will be in three state. ...
Page 32
... Sc is set. The only ways to reset this status bits through the RI signal or a general reset. If this status bit is active, it indicates that the TSS463AA has chosen an identifier to transmit, and it will continue to make transmission attempt for this message until it suc- ceeds or the retry count is exceeded ...
Page 33
... Zero: BOV inactive FCSE indicates a mismatch between the FCS received and the FCS calculated One: FCSE active Zero: FCSE inactive ACKE indicates a physical violation or collision on ACK field of the frame when the TSS463AA is a producer. One: ACKE active Zero: ACKE inactive TSS463-AA 4 ...
Page 34
... Sync” field. One: CV active Zero: CV inactive FV indicates a physical violation or collision on ACK field of the frame when the TSS463AA is a consumer. One: FV active Zero: FV inactive DLC: Producer ACK field ...
Page 35
... Zero: No status flag. This flag is set only when the Max number of transmission ( [3:0]) is reached with error of transmission. One: Status flag activated Zero: No status flag. Figure 25. Exceeded Retry with MR[3.. 1st TX 2nd TX TSS463-AA DLC: Consumer ACK field ACK field ...
Page 36
... TOKE: Transmission OK Enable REE: Reception Error Enable ROKE: Reception “with RAK” OK Enable RNOKE: Reception “with no RAK” OK Enable Interrupt Reset Register (0x0B): TSS463-AA 36 One: Status flag activated Zero: No status flag. One: Status flag activated Zero: No status flag. One: Status flag activated Zero: No status flag ...
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... TOK RE Flag Flag Write Write TOKE REE TER TOKR RER SOF ID+COM+DATA+CRC Write “Message Status” TSS463-AA ROK RNOK Flag Flag Write Write ROKE RNOKE ROKR RNOKR 6 TS Line Status Register (0x04 Write “IT Status Register” Write “Last error Register” ...
Page 38
... The base_address of each set is: (0x10 + [0x08 * channel_number]). When the TSS463AA is reset either via the external RESET pin or the general reset command, the channel registers are not affected. That is, on power-up of the circuit, all the channel registers start with random values. ...
Page 39
... However, the identifier, mask, error and transmitted status used will be that of the origi- nally matched channel. In any case link is intended, the three high bits of M_P [6:0] should be set to 0. TSS463- ...
Page 40
... The 2 low order bits of this register contain the message status. Together with the RNW and RTR bits of the command register (base_address + 0x01), they define the message type of this channel (see section “Message Types” on page 45 general rule, the status bits are only set by the TSS463AA, so the user must reset them to perform ...
Page 41
... ID_M 11 ID_M 10 ID_M 9 ID_M 8 • Read/Write registers. A value of 1 indicates comparison enabled. A value of 0 indicates comparison disabled. Example: – ID_M[11:0] = 0x0FF8 – Acceptance: ID’s from 0x0FF8 up to 0x0FFF TSS463- ID_M 7 ID_M 6 ID_M 5 ID_M 4 ...
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... M_L [4..0] SOF ID [11..0] Received DATA Frame, immediate or deffered reply TSS463-AA 42 The mailbox contains all the messages received transmitted. Each messages is link to a channel. The Mailbox RAM area has 128 bytes and is mapped from 0x80 to 0xFF (see Section “Mapping”, page 26 ). ...
Page 43
... This bit is the RNW bit coming from the COM field of the received frame. This bit is the RTR bit coming from the COM field of the received frame. If the DATA field of the received frame included DATA0 to DATAn, RM_L[4:0] = n+1, even if the reserved length (Message Length and Status Register) is larger. TSS463-AA Message Pointer Register M_P [6..0] DRAK ...
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... Note the length reserved (in the message length and status register) for an incoming frame is 2 bytes greater or more, the TSS463AA will write the 2 bytes of the CRC field in the message string just after DATAn. Because the VAN frame does not content a message length, the only way for the component to know the length of the DATA field is either the message length register value, either the EOD field detection ...
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... In the first case no other modules on the bus responded with an in-frame reply, and in this case the TSS463AA will set the message type to the after transmission state. When this message type is programmed, the TSS463AA will listen on the bus for a deferred reply frame matching this identifier, without transmitting the reply request. ...
Page 46
... After reception 1 In the third case the TSS463AA has not yet started to transmit the reply request, when another module either requests a reply, and gets it, or transmits a deferred reply. Warn- ing! This should be avoided as it may result in an illegal message type (Illegal reply Request) ...
Page 47
... The priority handling on the VAN bus itself is already explained in the Line interface sec- tion. The priorities for the messages in the TSS463AA is however slightly different. For instance, it’s possible that an identifier matches two or more of the identifiers pro- grammed into the registers. In this case the lowest identifier number that has priority ...
Page 48
... If Ch8 the retry loop and the user wants to transmit the Ch5 without waiting the end of the loop, the user can use the rearbitrate command. • The TSS463AA will then wait until the end of the current transmission, reload the retries counter and enable the Ch5 to transmit. • ...
Page 49
... If the user sets the idle bit anywhere (after rearbitrate), the idle mode is entered only at the end of all the transmit attempts (for more information about idle command, see “Activate, Idle and Sleep Modes” on page 52.). 4205B–AUTO–12/04 Delay EOF+IFS Viol Delay EOF+IFS Viol TSS463-AA stand-by Delay Viol EOF+IFS imeslots Delay Viol imeslots Idle Delay Viol ...
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... Figure 33. Disable Channel After Rearbitrate Delay Viol In this case, the TSS463AA completes the current attempt (Ch8) and let the transmission go on the new channel (Ch5 if validated), otherwise it stops all attempts on the current channel. Abort TSS463-AA 50 Ex: ACK Error (not seen by application) ...
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... Figure 34. Abort Example 4205B–AUTO–12/04 12 Timeslots TSS463-AA 51 ...
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... The TxD output (pin 12 tri-state mode, a pull-up resistor must be provided exter- nally or by the line driver to avoid floating state on the VAN bus. To activate the TSS463AA, the user must set the activate bit (ACTI) and reset the idle bit (IDLE). Activate Mode ...
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... All the others can be different between the two channels, for example the ID_Tag. The Channel j linked . . . . to the Channel i CHER CHTx CHRx i EXT RAK RNW RTR CHER CHTx CHRx Mess_Ptr EXT RAK RNW RTR TSS463-AA Channel i and j share the same Message area --- Message for Channels i & j --- DATA n DATA 0 Message Status 53 ...
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... Sleep Mode I is measured according CCSB 2. Active mode I is measured at: XTAL = 8 MHz clock, VAN speed rate = 125 KTS/s. CCOP function of the Clock Frequency. Figure 38 displays a graph showing RESET, RxD0, RxD1, RxD2 inputs. TSS463-AA 54 *NOTICE: +0. 10 Min ...
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... Figure 37 Figure 38. I versus Clock Frequency at 125 KTimeslot/s CCOP mA 9 8.5 8 7.5 TSS463-AA MHz ...
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... AC Characteristics SS (INPUT) SCLK (INPUT) MISO (OUTPUT) MOSI (INPUT) INT TSS463- - 125 10 Table 11. Microprocessor Interface C = 200pF on SPI/SCI Lines LOAD Symbol Characteristic Operating Frequency SPI f OP SCI Cycle Time SPI t CYC SCI t Enable Lead Time LEAD t Enable Lead Time ...
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... C1 (no capacitance needed) see Note: Symbol Parameter t Oscillator period CHCH t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL V IH XTAL1 TSS463-AA MHz Figure 5 Min Max 120 CHCL CLCH ...
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... Packaging Information SO16 TSS463- 2.35 A1 0.10 B 0.35 C 0.23 D 10.10 E 7.40 e 1.27 H 10.00 h 0. Inch 2.65 0.093 0.30 0.004 0.49 0.014 0.32 0.009 10.50 0.398 7.60 0.291 BSC 0.050 10.65 0.394 0.75 0.010 1.27 0.016 4205B–AUTO–12/04 0.104 0.012 0.019 0.013 0.413 0.299 BSC 0.419 0.029 0.050 ...
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... Ordering Information 4205B–AUTO–12/04 Part Number Supply Voltage TSS463-AA 5V +10% TSS463-AA +10% (1) TSS463A-TERZ 5V +10% Note: 1. These products are available in ROHS version. TSS463-AA Temperature Range Package -40°C to +125°C SO16 -40°C to +125°C SO16 -40°C - +125°C SO16 Packing Stick ...
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