IDT72261 IDT [Integrated Device Technology], IDT72261 Datasheet - Page 30

• Manufacturer Part Number: IDT72261
• Description: CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
• Manufacturer: IDT [Integrated Device Technology]

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
where T
the WCLK period, whichever is shorter.
from the inputs of the first FIFO to the outputs of the last FIFO
in the chain is the sum of the delays for each individual FIFO:
takes to pass data between FIFOs.
written to an empty depth expansion configuration. There will
be no delay evident for subsequent words written to the
configuration.
expansion configuration will "bubble up" from the last FIFO to
the previous one until it finally moves into the first FIFO of the
IDT
ORDERING INFORMATION
The maximum amount of time it takes for a word to pass
where N is the number of FIFOs in the expansion.
Note that the additional RCLK term accounts for the time it
The ripple down delay is only noticeable for the first word
The first free location created by reading from a full depth
Device Type
XXXXX
RCLK
t
FWL2(1)
is the RCLK period and T
+ t
FWL2(2)
Power
X
+ ... + t
Speed
XX
FWL2(N)
f
is either the RCLK or
Package
+ N*T
X
RCLK
Temperature
Process /
Range
X
chain. Each time a free location is created in one FIFO of the
chain, that FIFO's
FIFO to write a word to fill it.
to assert after a word is read from the last FIFO is the sum of
the delays for each individual FIFO:
is the WCLK period. Note that one of the three WCLK cycle
accounts for T
each FIFO in the chain. The Transfer Clock line should be tied
to either WCLK or RCLK, whichever is faster. Both these
actions result in moving, as quickly as possible, data to the
end of the chain and free locations to the beginning of the
chain.
where N is the number of FIFOs in the expansion and T
The amount of time it takes for
In a SuperSync depth expansion, set FS individually for
BLANK
B
G
PF
TF
10 Commercial Only
12 Commercial Only
15 Commercial & Military
20 Commercial Only
25 Military Only
L
72261
72271
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SKEW1
IR
Commercial (0 C to +70 C)
Military (–55 C to +125 C)
Compliant to MIL-STD-883, Class B
Pin Grid Array (PGA, G68-1)
Thin Plastic Quad Flatpack (TQFP, PN64-1)
Slim Thin Quad Flatpack (STQFP, PP64-1)
Low Power
16,384 x 9 SuperSync FIFO
32,768 x 9 SuperSync FIFO
line goes LOW, enabling the preceding
delays.
N*(3*T
IR
WCLK
of the first FIFO in the chain
Clock Cycle Time (t
Speed in Nanoseconds
)
3036 drw 27
CLK
WCLK
30
)