SST29EE010-120-3C-E SST [Silicon Storage Technology, Inc], SST29EE010-120-3C-E Datasheet - Page 2

• Manufacturer Part Number: SST29EE010-120-3C-E
• Description: 1 Megabit (128K x 8) Page Mode EEPROM
• Manufacturer: SST [Silicon Storage Technology, Inc]

chip is deselected and only standby power is consumed.
OE# is the output control and is used to gate data from
the output pins. The data bus is in high impedance state
when either CE# or OE# is high. Refer to the read cycle
timing diagram for further details (Figure 3).
Write
The Page Write to the SST29EE010/29LE010/29VE010
should always use the JEDEC Standard Software Data
Protection (SDP) 3-byte command sequence. The
29EE010/29LE010/29VE010 contain the optional
JEDEC approved Software Data Protection scheme.
SST recommends that SDP always be enabled, thus, the
description of the Write operations will be given using the
SDP enabled format. The 3-byte SDP Enable and SDP
Write commands are identical; therefore, any time a
SDP Write command is issued, software data protec-
tion is automatically assured. The first time the 3-byte
SDP command is given, the device becomes SDP en-
abled. Subsequent issuance of the same command
bypasses the data protection for the page being written.
At the end of the desired page write, the entire device
remains protected. For additional descriptions, please
see the application notes on “The Proper Use of JEDEC
Standard Software Data Protection” and “Protecting
Against Unintentional Writes When Using Single Power
Supply Flash Memories” in this data book.
The Write operation consists of three steps. Step 1 is the
three byte load sequence for Software Data Protection.
Step 2 is the byte-load cycle to a page buffer of the
29EE010/29LE010/29VE010. Steps 1 and 2 use the
same timing for both operations. Step 3 is an internally
controlled write cycle for writing the data loaded in the
page buffer into the memory array for nonvolatile stor-
age. During both the SDP 3-byte load sequence and the
byte-load cycle, the addresses are latched by the falling
edge of either CE# or WE#, whichever occurs last. The
data is latched by the rising edge of either CE# or WE#,
whichever occurs first. The internal write cycle is initiated
by the T
whichever occurs first. The write cycle, once initiated, will
continue to completion, typically within 5 ms. See Fig-
ures 4 and 5 for WE# and CE# controlled page write cycle
timing diagrams and Figures 14 and 16 for flowcharts.
The Write operation has three functional cycles: the
Software Data Protection load sequence, the page load
cycle, and the internal write cycle. The Software Data
Protection consists of a specific three byte load se-
quence that allows writing to the selected page and will
© 1998 Silicon Storage Technology, Inc.
BLCO
timer after the rising edge of WE# or CE#,
2
SST29EE010, SST29LE010, SST29VE010
leave the 29EE010/29LE010/29VE010 protected at the
end of the page write. The page load cycle consists of
loading 1 to 128 bytes of data into the page buffer. The
internal write cycle consists of the T
write timer operation. During the Write operation, the only
valid reads are Data# Polling and Toggle Bit.
The Page-Write operation allows the loading of up to 128
bytes of data into the page buffer of the 29EE010/
29LE010/29VE010 before the initiation of the internal
write cycle. During the internal write cycle, all the data in
the page buffer is written simultaneously into the memory
array. Hence, the page-write feature of 29EE010/
29LE010/29VE010 allow the entire memory to be written
in as little as 5 seconds. During the internal write cycle,
the host is free to perform additional tasks, such as to
fetch data from other locations in the system to set up the
write to the next page. In each Page-Write operation, all
the bytes that are loaded into the page buffer must have
the same page address, i.e. A
loaded with user data will be written to FF.
See Figures 4 and 5 for the page-write cycle timing
diagrams. If after the completion of the 3-byte SDP load
sequence or the initial byte-load cycle, the host loads a
second byte into the page buffer within a byte-load cycle
time (T
will stay in the page load cycle. Additional bytes are then
loaded consecutively. The page load cycle will be termi-
nated if no additional byte is loaded into the page buffer
within 200 µs (T
no subsequent WE# or CE# high-to-low transition after
the last rising edge of WE# or CE#. Data in the page
buffer can be changed by a subsequent byte-load cycle.
The page load period can continue indefinitely, as long
as the host continues to load the device within the byte-
load cycle time of 100 µs. The page to be loaded is
determined by the page address of the last byte loaded.
Software Chip-Erase
The 29EE010/29LE010/29VE010 provide a Chip-Erase
operation, which allows the user to simultaneously clear
the entire memory array to the “1” state. This is useful
when the entire device must be quickly erased.
The Software Chip-Erase operation is initiated by using
a specific six byte-load sequence. After the load se-
quence, the device enters into an internally timed cycle
similar to the write cycle. During the erase operation, the
only valid read is Toggle Bit. See Table 4 for the load
sequence, Figure 9 for timing diagram, and Figure 18 for
the flowchart.
BLC
) of 100 µs, the 29EE010/29LE010/29VE010
1 Megabit Page Mode EEPROM
BLCO
) from the last byte-load cycle, i.e.,
7
through A
BLCO
time-out and the
16
. Any byte not
304-04 12/97