DS3231S+ DALLAS [Dallas Semiconductor], DS3231S+ Datasheet - Page 13

• Manufacturer Part Number: DS3231S+
• Description: Extremely Accurate I2C-Integrated RTC/TXO/Crystal
• Manufacturer: DALLAS [Dallas Semiconductor]

The DS3231 has two additional registers (control and
status) that control the real-time clock, alarms, and
square-wave output.
Bit 7: Enable Oscillator (EOSC). When set to logic 0,
the oscillator is started. When set to logic 1, the oscilla-
tor is stopped when the DS3231 switches to V
bit is clear (logic 0) when power is first applied. When
the DS3231 is powered by V
on regardless of the status of the EOSC bit.
Bit 6: Battery-Backed Square-Wave Enable
(BBSQW). When set to logic 1 and the DS3231 is
being powered by the V
square-wave output when V
BBSQW is logic 0, the INT/SQW pin goes high imped-
ance when V
This bit is disabled (logic 0) when power is first applied.
Bit 5: Convert Temperature (CONV). Setting this bit to
1 forces the temperature sensor to convert the temper-
ature into digital code and execute the TCXO algorithm
to update the capacitance array to the oscillator. This
can only happen during the idle period. The status bit,
BSY, prevents the bit from being set when BSY = 1.
The user should check the status bit BSY before forcing
the controller to start a new TCXO execution. A user-ini-
tiated temperature conversion does not affect the inter-
nal 64-second update cycle.
A user-initiated temperature conversion does not affect
the BSY bit for approximately 2ms. The CONV bit
remains at a 1 from the time it is written until the conver-
sion is finished, at which time both CONV and BSY go
to 0. The CONV bit should be used when monitoring
the status of a user-initiated conversion.
Bits 4 and 3: Rate Select (RS2 and RS1). These bits
control the frequency of the square-wave output when
the square wave has been enabled. The following table
shows the square-wave frequencies that can be select-
ed with the RS bits. These bits are both set to logic 1
(8.192kHz) when power is first applied.
EOSC
BIT 7
Special-Purpose Registers
CC
BBSQW
falls below the power-fail trip point.
BIT 6
BAT
Control Register (0Eh)
CC
pin, this bit enables the
Extremely Accurate I
, the oscillator is always
CC
CONV
BIT 5
is absent. When
____________________________________________________________________
BAT
BIT 4
RS2
. This
Bit 2: Interrupt Control (INTCN). This bit controls the
INT/SQW signal. When the INTCN bit is set to logic 0, a
square wave is output on the INT/SQW pin. When the
INTCN bit is set to logic 1, then a match between the
timekeeping registers and either of the alarm registers
activates the INT/SQW (if the alarm is also enabled).
The corresponding alarm flag is always set regardless
of the state of the INTCN bit. The INTCN bit is set to
logic 1 when power is first applied.
Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to
logic 1, this bit permits the alarm 2 flag (A2F) bit in the
status register to assert INT/SQW (when INTCN = 1).
When the A2IE bit is set to logic 0 or INTCN is set to
logic 0, the A2F bit does not initiate an interrupt signal.
The A2IE bit is disabled (logic 0) when power is first
applied.
Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to
logic 1, this bit permits the alarm 1 flag (A1F) bit in the
status register to assert INT/SQW (when INTCN = 1).
When the A1IE bit is set to logic 0 or INTCN is set to
logic 0, the A1F bit does not initiate the INT/SQW sig-
nal. The A1IE bit is disabled (logic 0) when power is
first applied.
SQUARE-WAVE OUTPUT FREQUENCY
BIT 3
RS1
RS2
0
0
1
1
RTC/TCXO/Crystal
RS1
INTCN
0
1
0
1
BIT 2
Control Register (0Eh)
2
C-Integrated
SQUARE-WAVE OUTPUT
BIT 1
A2IE
FREQUENCY
1.024kHz
4.096kHz
8.192kHz
1Hz
BIT 0
A1IE
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