DS3231S+ DALLAS [Dallas Semiconductor], DS3231S+ Datasheet - Page 16

• Manufacturer Part Number: DS3231S+
• Description: Extremely Accurate I2C-Integrated RTC/TXO/Crystal
• Manufacturer: DALLAS [Dallas Semiconductor]

Extremely Accurate I
RTC/TCXO/Crystal
Figures 3 and 4 detail how data transfer is accom-
plished on the I
the R/W bit, two types of data transfer are possible:
The DS3231 can operate in the following two modes:
Figure 2. I
16
SDA
SCL
Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after
each received byte. Data is transferred with the most
significant bit (MSB) first.
Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is trans-
mitted by the master. The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last
received byte, a not acknowledge is returned.
The master device generates all the serial clock puls-
es and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated
START condition. Since a repeated START condition
is also the beginning of the next serial transfer, the
bus will not be released. Data is transferred with the
most significant bit (MSB) first.
Slave receiver mode (DS3231 write mode): Serial
data and clock are received through SDA and SCL.
After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are recog-
nized as the beginning and end of a serial transfer.
CONDITION
START
____________________________________________________________________
2
C Data Transfer Overview
MSB
2
C bus. Depending upon the state of
1
2
SLAVE ADDRESS
6
7
DIRECTION
R/W
BIT
8
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
2
C-Integrated
ACK
9
Figure 3. Slave Receiver Mode (Write Mode)
Figure 4. Slave Transmitter Mode (Read Mode)
Address recognition is performed by hardware after
reception of the slave address and direction bit. The
slave address byte is the first byte received after the
master generates the START condition. The slave
address byte contains the 7-bit DS3231 address,
which is 1101000, followed by the direction bit (R/W),
which is 0 for a write. After receiving and decoding
the slave address byte, the DS3231 outputs an
S = START
A = ACKNOWLEDGE
P = STOP
R/W = READ/WRITE OR DIRECTION BIT ADDRESS = D0H
S = START
A = ACKNOWLEDGE
P = STOP
A = NOT ACKNOWLEDGE
R/W = READ/WRITE OR DIRECTION BIT ADDRESS = D1H
S
S
ADDRESS>
ADDRESS>
<SLAVE
<SLAVE
1101000
1101000
1
0
1
A
A
ADDRESS (n)>
<DATA (n)>
XXXXXXXX
XXXXXXXX
2
REPEATED IF MORE BYTES
<WORD
ARE TRANSFERED
3–7
A
A
NOTE: LAST DATA BYTE IS FOLLOWED BY
<DATA (n + 1)>
SIGNAL FROM RECEIVER
<DATA (n)>
XXXXXXXX A XXXXXXXX A XXXXXXXX A P
XXXXXXXX A XXXXXXXX A XXXXXXXX A P
ACKNOWLEDGEMENT
(X + 1 BYTES + ACKNOWLEDGE)
(X + 1 BYTES + ACKNOWLEDGE)
8
A NOT ACKNOWLEDGE (A) SIGNAL
DATA TRANSFERRED
DATA TRANSFERRED
<DATA (n + 1)>
<DATA (n + 2)>
ACK
9
<DATA (n + X)>
<DATA (n + X)>
OR REPEATED
CONDITION
CONDITION
START
STOP