ISL1903EVAL2Z INTERSIL [Intersil Corporation], ISL1903EVAL2Z Datasheet - Page 6

• Manufacturer Part Number: ISL1903EVAL2Z
• Description: Dimmable Buck LED Driver - AC Mains or DC Input LED Driver
• Manufacturer: INTERSIL [Intersil Corporation]

Pin Descriptions
Pin Configuration
PIN #
10
11
12
13
14
1
2
3
4
5
6
7
8
9
SYMBOL
OFFREF
DELADJ
RAMP
VERR
VREF
IOUT
GND
DHC
VDD
CS+
OVP
OC
AC
FB
VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to
the VDD and GND pins as possible.
Sets the reference level to disable the driver at light loading. The turn-off reference can be set at any level between 0 and 0.6V,
corresponding to 0 to 100% of output loading. This feature is normally used in triac-based wall dimmer applications to disable
the output before the dimmer becomes unstable due to insufficient holding current.
The 5.40V reference voltage output having ±100 mV tolerance over line, load and operating temperature. Bypass to GND with
a 0.1µF to 3.3µF low ESR capacitor.
A voltage signal proportional to the peak switching current used to determine the inductor current.
The input for the CrCM current sense circuit. This input monitors the winding current or voltage to determine the critical
conduction operating point.
The input to the load current sensing circuitry and the peak overcurrent comparator. The signal is sampled at the peak current
level for each switching cycle, amplified, and output on IOUT as a DC signal. It must be scaled before application to the FB pin
of the error amplifier (EA). The overcurrent comparator threshold is set at 600mV nominal. Peak OCP performs cycle-by-cycle
over current protection. OCP includes leading-edge-blanking (LEB), which blocks the signal at the beginning of the OUT pulse
for the duration of the blanking period and when the OUT pulse is low.
FB is the inverting input to the error amplifier (EA). The feedback signal from IOUT, after being scaled and filtered, is applied
to the error amplifier.
Sets delay before a new switching cycles starts. This adjustment allows the user to delay the next switching cycle until the
switching FET drain-source voltage reaches a minimum value to allow quasi-ZVS (Zero Voltage Switching) operation. A resistor
to ground programs the delay. Pulling DELADJ to VREF disables the CrCM oscillator.
Output of the error amplifiers and the control voltage input to the inverting input of the PWM comparator. VERR cannot source
current and requires an external pull-up resistor to VREF.
This is the input for the sawtooth waveform for the PWM comparator. Using an RC from VREF, a sawtooth waveform is created
for use by the PWM. It is compared to the error amplifier output, Verr, to create the PWM control signal. The RAMP pin is shorted
to GND at the termination of the PWM signal.
Input to detect an overvoltage (OV) condition on the output. Since the control variable is output current, a fault that results in
an open circuit will cause excessive output voltage. The circuit hysteresis is a switched current source that is active when the
OV threshold is exceeded.
Input to sense AC voltage presence and amplitude. A resistor divider from the main FET drain and circuit ground or from an
auxiliary winding on the transformer/inductor is used to detect the AC voltage.
Signal and power ground connections for this device. Due to high peak currents and high frequency operation, a low impedance
layout is necessary. Ground planes and short traces are highly recommended.
An open drain FET used to load the input voltage to pre-load a triac-based dimmer so that adequate holding current is
maintained.
6
1
2
3
4
5
6
7
8
ISL1903
VDD
OFFREF PWMOUT
VREF
IOUT
CS+
OC
FB
DELADJ
(16 LD QSOP)
TOP VIEW
ISL1903
RAMP
VERR
GND
DHC
OUT
OVP
DESCRIPTION
AC
16
15
14
13
12
11
10
9
September 20, 2012
FN8285.1