ls7211 LSI Computer Systems, Inc., ls7211 Datasheet

no-image

ls7211

Manufacturer Part Number
ls7211
Description
Programmable Digital Delay Timer
Manufacturer
LSI Computer Systems, Inc.
Datasheet
7211-110503-1
FEATURES:
• 8-bit programmable delay from microseconds to days
• On chip oscillator (RC or Crystal) or external clock time base
• Selectable prescaler for real time delay generation based
• Four operating modes
• Reset input for delay abort
• Low quiescent and operating current
• Direct relay drive
• +4V to +18V operation (V
• LS7211, LS7212 (DIP); LS7211-S, LS7212-S (SOIC) - See Figure 1
DESCRIPTION:
The LS7211 and LS7212 are CMOS integrated circuits for
generating digitally programmable delays. The
controlled by 8 binary weighted inputs, WB0 - WB7, in con-
junction with an applied clock or oscillator frequency. The
programmed time delay manifests itself in the Delay Output
(OUT) as a function of the Operating Mode selected by the
Mode Select inputs A and B: One-Shot, Delayed Operate,
Delayed Release or Dual Delay. The time delay is initiated
by a transition of the Trigger Input (TRIG).
I/O DESCRIPTION:
MODE SELECT Inputs A & B (Pins 1 & 2)
The 4 operating modes are selected by Inputs A and B
according to Table 1
Each input has an internal pull-up resistor of about 500k .
One-Shot Mode (OS)
A positive transition at the TRIG input causes OUT to
switch low without delay and starts the delay timer. At the
end of the programmed delay timeout, OUT switches high.
If a delay timeout is in progress when a positive transition
occurs at the TRIG input, the delay timer will be restarted.
A negative transition at the TRIG input has no effect.
Delayed Operate Mode (DO)
A positive transition at the TRIG input starts the delay tim-
er. At the end of the delay timeout, OUT switches low. A
negative transition at the TRIG input causes OUT to switch
high without delay. OUT is high when TRIG is low.
LSI/CSI
U L
A3800
on 50Hz/60Hz time base or 32.768kHz watch crystal
®
A
0
0
1
1
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
TABLE 1. MODE SELECTION
B
0
1
0
1
PROGRAMMABLE DIGITAL DELAY TIMER
DD
MODE
One-Shot (OS)
Delayed Operate (DO)
Delayed Release (DR)
Dual Delay (DD)
- V
SS
)
delay is
Delayed Release Mode (DR)
A negative transition at the TRIG input starts the delay tim-
er. At the end of the delay timeout, OUT switches high. A
postive transition at the TRIG input causes OUT to switch
low without delay. OUT is low when TRIG is high.
Dual Delay Mode (DD)
A positive or negative transition at the TRIG input starts
the delay timer. At the end of the delay timeout, OUT
switches to the logic state which is the inverse of the TRIG
input. If a delay timeout is in progress when a transition
occurs at the TRIG input, the delay timer is restarted.
XTLI/CLOCK
RC/CLOCK
RCS/CLKS
LS7211-7212
V
V
V
V
R E S E T
DD
R E S E T
P S C L S
P S C L S
DD
SS
SS
XTLO
OUT
OUT
(+V)
(-V)
(-V)
(+V)
(631) 271-0400 FAX (631) 271-0405
A
B
A
B
PIN ASSIGNMENT - TOP VIEW
2
4
6
9
1
3
5
7
8
1
2
4
6
8
9
3
5
7
FIGURE 1
18
17
16
15
14
13
12
11
10
18
17
16
15
14
13
12
11
10
November 2003
TRIG
TRIG
WB0
WB1
WB2
WB3
WB4
WB5
WB6
WB7
WB0
WB1
WB2
WB3
WB4
WB5
WB6
WB7

Related parts for ls7211

ls7211 Summary of contents

Page 1

... Direct relay drive • +4V to +18V operation ( • LS7211, LS7212 (DIP); LS7211-S, LS7212-S (SOIC) - See Figure 1 DESCRIPTION: The LS7211 and LS7212 are CMOS integrated circuits for generating digitally programmable delays. The controlled by 8 binary weighted inputs, WB0 - WB7, in con- junction with an applied clock or oscillator frequency ...

Page 2

... Schmitt trigger to provide input hysterisis. LS7211 TIME BASE Input (RC/CLOCK, Pin 4) For LS7211, the basic timing signal is applied at the RC/ CLOCK input. The clock can be provided from either an ex- ternal source or generated by an internal oscillator by con- necting an R-C network to this input. ...

Page 3

ABSOLUTE MAXIMUM RATINGS: (All voltages referenced Supply Voltage Voltage (Any Pin) Operating Temperature Storage Temperature ELECTRICAL CHARACTERISTICS (Voltages referenced to Vss) Characteristic SYMBOL Supply Voltage V DD Supply Current I DD Input Voltages: Trigger Low V Trigger ...

Page 4

... MODE REG EDGE DETECT LATCH 500K CLOCK MUX OSC +V 1M 3-STATE DECODER 1M FIGURE 2. LS7211/LS7212 BLOCK DIAGRAM Unit Condition Max Min Max 1.0 - 0.76 MHz 3.0 - 2.3 MHz - 4.5 - 3.4 MHz 1.8 - 1.3 MHz For prescale 5.5 - 4.0 MHz factor 3000 8.5 - 6.5 MHz or 3600 0.93 - ...

Page 5

Clock t 1 TRIG Delayed Operate A WB0-WB7 OUT Note 1. TRIG input is clocked in by the negative edge of external clock. Note 2. Inputs A, B ...

Page 6

10K ƒ µ ƒ ...

Page 7

TRIGGER IN 25pF ƒ 25pF 470K + OUTPUT NOTE : Crystal Frequency, ƒ = 32,768Hz FIGURE 9. PROGRAMMABLE ACCURATE REAL-TIME DELAY GENERATION 7211-012703 TRIG 4 XTLI 10M 5 XTLO 6 PSCLS LS7212 7 ...

Page 8

CASE 1. MODE = DO or DR; PRESCALE FACTOR this setup a frequency division of the input clock, ƒ factor 257, in increments of 1 can be obtained ...

Related keywords