ISL28210 INTERSIL [Intersil Corporation], ISL28210 Datasheet
ISL28210
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ISL28210 Summary of contents
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... The ISL28110 single amplifier is available in the 8 Ld SOIC, TDFN, and MSOP packages. The ISL28210 dual amplifier is available in the 8 Ld SOIC and TDFN packages. All devices are offered in standard pin configurations and operate over the extended temperature range from -40° ...
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... Ld SOIC, ISL28210 (8 Ld TDFN MSOP TDFN PAD V + IN- IN CIRCUIT 1 2 ISL28110, ISL28210 ISL28110, ISL28210 OUT OUT - +IN B ISL28210 PIN (8 Ld SOIC) NAME ...
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... PKG. (Pb-free) DWG SOIC M8.15E 8 Ld SOIC M8.15E 8 Ld TDFN L8.3x3A 8 Ld TDFN L8.3x3A 8 Ld TDFN L8.3x3A 8 Ld TDFN L8.3x3A 8 Ld SOIC M8.15E 8 Ld SOIC M8.15E 8 Ld MSOP M8.118 8 Ld MSOP M8.118 ISL28110, ISL28210. For more information on December 8, 2010 FN6639.1 ...
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... IN-DIFF 4 ISL28110, ISL28210 ISL28110, ISL28210 Thermal Information Thermal Resistance (Typical SOIC (Notes 5, 7) ISL28110 . . . . . . . . . . . . . . . . . - 0. 0.5V ISL28210 . . . . . . . . . . . . . . . . . - + 8 Ld TDFN (Notes 4, 6) ISL28110 . . . . . . . . . . . . . . . . . ISL28210 . . . . . . . . . . . . . . . . . 8 Ld MSOP (Notes 5, 7) ISL28110 . . . . . . . . . . . . . . . . . Ambient Operating Temperature Range . . . -40°C to +125°C Storage Temperature Range . . . . . . . . . . . -65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . +150° ...
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... OH I Output Short Circuit Current SC POWER SUPPLY V Supply Voltage Range SUPPLY PSRR Power Supply Rejection Ratio I Supply Current/Amplifier S 5 ISL28110, ISL28210 ISL28110, ISL28210 = ±5V 0V +25°C, unless otherwise noted. Boldface limits apply S CM OUT A CONDITIONS Guaranteed by CMRR test V = -3.5V to +3. ...
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... OUT THD+N Total Harmonic Distortion + Noise t Settling Time to 0.1% s 10V Step; 10 OUT Settling Time to 0.01% 10V Step; 10 OUT 6 ISL28110, ISL28210 ISL28110, ISL28210 = ±15V 0V +25°C, unless otherwise noted. Boldface limits apply CONDITIONS -40°C < T < +125°C A -40° ...
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... POWER SUPPLY PSRR Power Supply Rejection Ratio I Supply Current/Amplifier S NOTE: 8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7 ISL28110, ISL28210 ISL28110, ISL28210 = ±15V 0V +25°C, unless otherwise noted. Boldface limits apply CONDITIONS 0.1Hz to 10Hz ...
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... V = ±15V -400 S -500 -600 -700 -800 -900 -1000 -1100 -40 - TEMPERATURE (°C) FIGURE 5. ISL28210 INPUT BIAS CURRENT (I TEMPERATURE 8 ISL28110, ISL28210 ISL28110, ISL28210 V = ±15V 0V specified ±15V 100 150 200 250 ) FIGURE 2. T ...
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... Typical Performance Curves ± -10 I CHB OS -20 -40 - TEMPERATURE (°C) FIGURE 7. ISL28210 INPUT OFFSET CURRENT (I TEMPERATURE ± ±5V S 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1 (V) CM FIGURE 9. NORMALIZED INPUT BIAS CURRENT (I INPUT COMMON MODE VOLTAGE ( ±5V S 500 400 ...
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... FREQUENCY (Hz) FIGURE 17. THD+N vs FREQUENCY vs TEMPERATURE 10 10V V OUT 10 ISL28110, ISL28210 V = ±15V 0V specified. (Continued) 1000 1000 100 100 10k 100k 0.1 ) AND CURRENT FIGURE 14. INPUT NOISE VOLTAGE (e ...
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... GAIN 0 -20 - ±15V - =1MΩ -80 L -100 0 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 23. OPEN LOOP GAIN-PHASE vs FREQUENCY 11 ISL28110, ISL28210 V = ±15V 0V specified. (Continued 0.1 0.01 +25°C 0.001 +125°C -40°C 0.0001 FIGURE 20. THD+N vs OUTPUT VOLTAGE (V OUT = 600Ω ...
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... S 200 INPUT 160 120 OUTPUT TIME (µs) FIGURE 29. POSITIVE OUTPUT OVERLOAD RECOVERY TIME 12 ISL28110, ISL28210 V = ±15V 0V specified. (Continued) 130 120 110 PSRR- 100 100k 1M 10M FIGURE 26. COMMON-MODE REJECTION RATIO (CMRR) ...
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... S 0. ±15V 0. 4pF L 0.05 0 -0.05 -0.10 -0.15 0 0.1 0.2 0.3 0.4 0.5 TIME (µs) FIGURE 35. SMALL SIGNAL TRANSIENT RESPONSE 13 ISL28110, ISL28210 V = ±15V 0V specified. (Continued -10 FIGURE 32. SLEW RATE vs INVERTING CLOSED LOOP FIGURE 34. SLEW RATE vs NON-INVERTING CLOSED - ...
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... CLOSED LOOP GAIN S Applications Information Functional Description The ISL28110 and ISL28210 are single and dual 12.5 MHz precision JFET input op amps. These devices are fabricated in the PR40 Advanced Silicon-on-Insulator (SOI) bipolar-JFET process to ensure latch-free operation. The precision JFET input stage provides low input offset voltage (300µ ...
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... RRO -100 op amps can be lower than a good emitter follower output stage. -200 -300 The ISL28110 and ISL28210 low noise input stage and -400 high performance output stage are optimized for low -500 THD+N into moderate loads over the full -40° ...
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... R = Load resistance L 16 ISL28110, ISL28210 ISL28110 and ISL28210 SPICE Model Figure 44 shows the SPICE model schematic and Figure 45 shows the net list for the SPICE model. The model is a simplified version of the actual device and +125°C simulates important AC and DC parameters. AC ...
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V2 V2 0.7Vdc 0.7Vdc 5.5k 5.5k 9 PNP_MIRROR PNP_MIRROR Vin buffer1 buffer1 + + - + - + - - 0.4 0 5e11 5e11 NPN_CASCODE NPN_CASCODE D1 ...
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... VC VMID 1 * *1st Gain Stage * R_R8 18 V++ 100 D_D4 V-- 18 DBREAK D_D5 22 V++ DX D_D6 V V_V4 22 23 1.18 V_V5 23 24 1.18 18 ISL28110, ISL28210 G_G1 V G_G2 V R_R9 23 V++ 1 R_R10 V R_R11 D_D7 25 VMID DX D_D8 VMID 25 DX R_R12 25 VMID 1e10 G_G3 V VMID 181 ...
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... V 0. 4pF L 0.05 0 -0.05 -0.10 -0.15 0 0.1 0.2 0.3 0.4 0.5 TIME (µs) FIGURE 50. CHARACTERIZED SMALL SIGNAL TRANSIENT RESPONSE vs R ±2.5V 19 ISL28110, ISL28210 1000 1000 100 100 10k 100k FIGURE 47. SIMULATED INPUT NOISE VOLTAGE 70 = 100Ω 1kΩ ±5V & ±15V 4pF L ...
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... V = ±15V 20 S SIMULATION 100 1k 10k FREQUENCY (Hz) FIGURE 56. SIMULATED (DESIGN) CMRR 20 ISL28110, ISL28210 - FIGURE 53. SIMULATED LARGE SIGNAL TRANSIENT , V = ±0.9V 200 180 160 140 120 100 -20 -40 ...
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... Characterization vs Simulation Results 5 ±5V S -5.0 0.2 0.4 0 TIME (m s) FIGURE 58. SIMULATED OUTPUT VOLTAGE SWING ±5V 21 ISL28110, ISL28210 15V 10V 5V 0V -5V -10V -15V 0.6 0.8 1.0 FIGURE 59. SIMULATED OUTPUT VOLTAGE SWING ±15V (Continued) 0.2 0.4 0.6 0 TIME (m s) 0.8 1.0 FN6639.1 December 8, 2010 ...
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... Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 22 ISL28110, ISL28210 CHANGE B OS www.intersil.com/askourstaff www ...
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... LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 2/10 3.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW 2X 1.950 PIN #1 1 INDEX AREA 0.30 ± 0.10 2.30 ±0.10 BOTTOM VIEW 23 ISL28110, ISL28210 A B (1.50) ( 2.90 ) PIN 1 (6x 0.65) TYPICAL RECOMMENDED LAND PATTERN 0.75 ±0.05 6X 0.65 1.50 ±0. 0.30 ±0.05 0. NOTES: 1. Dimensions are in millimeters. ...
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... M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 3, 3/10 3.0±0. PIN TOP VIEW H 0.25 - 0.036 0. SIDE VIEW 1 (5.80) (4.40) (3.00) (0.65) TYPICAL RECOMMENDED LAND PATTERN 24 ISL28110, ISL28210 5 D 1.10 MAX 4.9±0.15 3.0±0.05 5 0.65 BSC 0.85±010 C SEATING PLANE 0.10 C 0.10 ± 0.05 NOTES (0.40) (1.40 SIDE VIEW 2 0.95 REF ...
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... M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 PIN NO.1 ID MARK 5 1.27 TOP VIEW 1.75 MAX 0.175 ± 0.075 SIDE VIEW “A (1.27) (5.40) TYPICAL RECOMMENDED LAND PATTERN 25 ISL28110, ISL28210 A DETAIL "A" B 6.0 ± 0.20 3.90 ± 0.10 4 (0.35) x 45° 0.43 ± 0.076 0. 1.45 ± 0.1 (0.60) NOTES: (1.50) 1 ...