AD625 AD [Analog Devices], AD625 Datasheet
AD625
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AD625 Summary of contents
Page 1
... An additional three resistors allow the user to set any gain from 1 to 10,000. The error contribution of the AD625JN is less than 0.05% gain error and under 5 ppm/°C gain TC; performance limitations are primarily determined by the external resistors. ...
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... V ± 650 650 400 400 150 150 25 25 5.0 5 and unless otherwise noted) A AD625C Max Min Typ Max 10,000 1 110,000 ± 0.01 0.03 0.02 ± 0.002 ± 0.001 ± 0.008 ± 0.005 5 5 250 ...
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... POWER SUPPLY Power Supply Range Quiescent Current NOTES 1 Gain Error and Gain TC are for the AD625 only. Resistor Network errors will add to the specified errors the maximum differential input voltage for specified nonlinearity – (10/2 × 0. 9.5 V. ...
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... CONNECT Operating Temperature Range AD625J 0°C to +70°C AD625A/B –40°C to +85°C AD625S . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C S Lead Temperature Range (Soldering 10 sec +300°C S *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied ...
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... FREQUENCY – Hz Ω – 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 WARM-UP TIME – Minutes Typical Performance Characteristics–AD625 SUPPLY VOLTAGE – 100 20 BANDWIDTH LIMITED G = 500 100 G = 1000 0 1k 10k 100k 1M FREQUENCY – Hz 160 – ...
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... S V OUT AD625 10V –V S 1000 100 100, 1000 G = 1000 1 0 100 1k 10k 100k FREQUENCY – –V S AD625 DUT 16. AD712 1/2 1/2 AD712 16.2k 9.09k 1 F – 10, 100 G = 1000 1.62M 100 1k 1.82k 100k 10k 1k 100 10 ...
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... – 1000 G = 100 – OUTPUT STEP – – 100 G = 1000 8 TO – – SETTLING TIME – S 10k 1k 10k 1% 10T 1% V OUT INPUT +V 100k S 20V p-p 0.1% AD625 1k 500 200 0.1% 0.1% 0.1% –V S AD625 70 ...
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... During differential overload conditions, excess current will flow through the gain sense lines (Pins 2 and 15). This will have effect in fixed gain applications. However, if the AD625 is being F G used in an SPGA application with a CMOS multiplexer, this current should be taken into consideration. The current capa- ...
Page 9
... Any resistors in series with the inputs of the AD625 will degrade the noise performance. For this reason the circuit in Figure 26b should be used if the gains are all greater than 5. For gains less than 5, either the circuit in Figure 26a or in Figure 26c can be used. The two 1.4 kΩ ...
Page 10
... By using an external power boosting circuit, the power dissipated by the AD625 will remain low, thereby, minimizing the errors induced by self- heating. The effects of nonlinearities, offset and gain inaccura- cies of the buffer are reduced by the loop gain of the AD625’s output amplifier ...
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... Total Error RTI = input error + (output error/gain) Total Error RTO = (Gain × input error) + output error The AD625 provides for both input and output offset voltage adjustment. This simplifies nulling in very high precision appli- cations and minimizes offset voltage effects in switched gain applications ...
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... This means that care must be taken to insure that all connections (especially those in the input circuit of the AD625) remain isothermal. This includes the input leads (1, 16) and the gain sense lines (2, 15). These pins were chosen for symmetry, helping to desensitize the input circuit to thermal gradients ...
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... Figure 38 shows an AD625 based SPGA with possible gains 16, 64. R equals the resistance between the gain sense G lines (Pins 2 and 15) of the AD625. In Figure 38, R the sum of the two 975 Ω resistors and the 650 Ω resistor, or 2600 Ω. R equals the resistance between the gain sense and the ...
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... AD625 1000 800 400 R 200 100 500 GAIN DETERMINING SPGA RESISTOR NETWORK VALUES The individual resistors in the gain network can be calculated sequentially using the formula given below. The equation deter- mines the resistors as labeled in Figure 41. The feedback resis- tors and the gain setting resistors are interactive, therefore ...
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... REF 0.025 0.003 1 (0.635 0.075) BOTTOM VIEW 0.050 (1.27 0.040 45° (1.02 45°) REF 3 PLCS AD625 16-Lead Ceramic DIP (D-16) 0.430 (10.922) 9 0.265 0.290 0.010 (7.37 0.254) (6.73) 8 0.800 0.010 0.300 20.32 0.254 (7.62) 0.035 0.01 REF (0.889 0.254) 0.085 (2.159) 0.180 0.03 (4.57 0.762) ...