74HCT00D,652 NXP Semiconductors, 74HCT00D,652 Datasheet - Page 11

IC GATE NAND QUAD 2INPUT 14SOIC

74HCT00D,652

Manufacturer Part Number
74HCT00D,652
Description
IC GATE NAND QUAD 2INPUT 14SOIC
Manufacturer
NXP Semiconductors
Series
74HCTr
Datasheet

Specifications of 74HCT00D,652

Number Of Circuits
4
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Logic Type
NAND Gate
Number Of Inputs
2
Current - Output High, Low
4mA, 4mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Product
NAND
Propagation Delay Time
10 ns
Supply Voltage (max)
5.5V
Supply Voltage (min)
4.5 V
Mounting Style
SMD/SMT
Logic Family
HCT
Logical Function
NAND
Number Of Elements
4
High Level Output Current
-4mA
Low Level Output Current
4mA
Operating Supply Voltage (typ)
5V
Operating Temp Range
-40C to 125C
Package Type
SO
Number Of Outputs
1
Technology
CMOS
Mounting
Surface Mount
Pin Count
14
Operating Temperature Classification
Automotive
Quiescent Current
40uA
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4993
74HCT00D
74HCT00D,652
74HCT00D
933713370652
NXP Semiconductors
Fig 11. Package outline SOT402-1 (TSSOP14)
74HC_HCT00
Product data sheet
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
UNIT
mm
VERSION
OUTLINE
SOT402-1
max.
1.1
A
0.15
0.05
A
1
0.95
0.80
14
A
1
2
y
IEC
Z
0.25
A
pin 1 index
e
3
D
0.30
0.19
b
p
All information provided in this document is subject to legal disclaimers.
MO-153
JEDEC
0.2
0.1
c
b
p
8
7
REFERENCES
Rev. 5 — 25 November 2010
D
5.1
4.9
0
(1)
w
M
E
4.5
4.3
(2)
JEITA
scale
2.5
0.65
e
c
A
H
6.6
6.2
2
E
A
1
5 mm
L
1
0.75
0.50
L
H
p
74HC00; 74HCT00
E
E
detail X
0.4
0.3
Q
L
L
PROJECTION
EUROPEAN
p
0.2
v
Q
Quad 2-input NAND gate
A
(A )
0.13
3
w
X
θ
v
0.1
A
© NXP B.V. 2010. All rights reserved.
y
M
ISSUE DATE
A
99-12-27
03-02-18
0.72
0.38
Z
(1)
SOT402-1
8
0
θ
o
o
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