ht48c50-1 Holtek Semiconductor Inc., ht48c50-1 Datasheet - Page 21
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ht48c50-1
Manufacturer Part Number
ht48c50-1
Description
Ht48r50a-1/ht48c50-1 -- I/o Type 8-bit Mcu
Manufacturer
Holtek Semiconductor Inc.
Datasheet
1.HT48C50-1.pdf
(41 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ht48c50-1-DBPF
Manufacturer:
HOLTEK
Quantity:
500
Note:
Rev. 2.00
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Mnemonic
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
(1)
(2)
(3)
(4)
: Flag is affected
: Flag is not affected
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
:
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
(1)
(four system clocks).
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
Otherwise the TO and PDF flags remain unchanged.
CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared.
and
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
(2)
Description
21
HT48R50A-1/HT48C50-1
Instruction
Cycle
1
1
1
1
1
1
1
1
2
2
1
1
1
2
2
2
2
2
1
1
1
1
1
1
(2)
(2)
(2)
(2)
(3)
(3)
(2)
(2)
(1)
(1)
(1)
(1)
(1)
March 8, 2006
TO
TO
Affected
TO,PDF
TO,PDF
(4)
(4)
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Flag
,PDF
,PDF
(4)
(4)