cxa2025as Sony Electronics, cxa2025as Datasheet - Page 30

• Manufacturer Part Number: cxa2025as
• Description: Y/c/rgb/sync/deflection For Color Tv
• Manufacturer: Sony Electronics

2) H deflection signal processing
The H pulse obtained through sync processing is phase-compared with the H deflection pulse input from Pin
36 to control the phase of the HDRIVE output and the horizontal position of the image projected on the CRT.
In addition, the compensation signal generated from the V sawtooth wave changes the phase of HDRIVE.As a
result,the vertical picture distortion is compensated.
The H deflection pulse is used to H blank the video signal. When the pulse input from Pin 36 has a narrow
width, the pulse generated by the IC can be added to the H deflection pulse and used as the H blanking pulse.
(HBLKSW)
Pin 36 is normally pulse input, but if the pin voltage drops to the GND level, HDRIVE output goes to high level
(DC) and 1 is output to the status register (HNG). To release this status, turn the power off and then on again.
3) V deflection signal processing
The V sawtooth wave is generated at the cycle of the reset pulse output from the countdown system. After
performing wide deflection processing for this sawtooth wave, picture distortion adjustment is performed by the
VDRIVE and E/WDRIVE function circuits and the signal is output as the VDRIVE and E/WDRIVE signals.
4) Y signal processing
The Y signal input to Pin 4 (specified input level: level at which a 100% white (including sync, 140 IRE) signal
with a gain of 6dB with respect to the video signal standard becomes a 2Vp-p signal) passes through the
subcontrast control, trap for eliminating the chroma signal, sharpness control, clamp and black expansion
circuits, and is then input to the switching circuit (YUV SW) for the external Y/color difference signal. The
differential waveform of the Y signal delayed for approximately 200ns from the Y input is output from Pin 45 as
the signal for VM.
The VM signal is not output in the following cases.
The f0 of the built-in filter is automatically adjusted inside the IC, but the trap f0 may require fine adjustment by
the I
by a comb filter, etc., the trap should be turned OFF.
5) C signal processing
The chroma signal input to Pin 5 (specified input level: level at which a 40 IRE burst level signal with a gain of
6dB with respect to the video signal standard becomes a 570mVp-p signal) passes through the ACC, TOT
(secondary HPF), color control and demodulation circuits. The signal then becomes the R-Y and B-Y color
difference signal and is input to the YUV SW circuit. When the burst level goes to –31dB or less with respect to
the specified input level, the color killer operates and the color difference signal is not output.
The external Y, color difference signals input to Pins 10, 11 and 12 passes through the clamp and amplifier
circuits and are input to the YUV SW circuit. The YUV SW circuit is controlled by the YUV SW (Pin 9).
However, its operation differs depending on the data in the I
SW circuit output is as follows.
When external Y/color difference signal is selected , the picture quality can be adjusted in the same manner as
with the normal internal Y signal by setting EY-SW to 1 and then inputting the external Y signal to YIN (Pin 4).
However, in this case the relative time difference between the Y and color difference signals must be
realigned.
The specified input level for the external Y signal is the level at which a normal video signal standard, 100 IRE,
100% white signal becomes a 0.7Vp-p signal. The specified input level for the external color difference signal
is the level at which a normal video signal standard, 40 IRE burst level demodulates a 258mVp-p chroma
signal at orthogonal coordinates to become a 0.8 times signal (R-Y is demodulated by the 90° axis to become
a 1.14 times signal, B-Y is demodulated by the 0° axis to become a 2.03 times signal).
When EY-SW = 0 and YUV SW (Pin 9) or YS (Pin 15) = high
When EY-SW = 1 and YS (Pin 15) = high
When EY-SW = 0: Internal Y/color difference signal when YUV SW = low,
When EY-SW = 1: Internal Y/color difference signal when YUV SW = low,
2
C bus (CTRAP-ADJ) if it is affected by variation. When inputting a signal which has been Y/C separated
external Y/color difference signal (Pins 9, 10 and 11) when YUV SW = high
internal Y/external color difference signal when YUV SW = high
– 30 –
2
C bus register (EY-SW). In other words, the YUV
CXA2025AS