cxa2076q Sony Electronics, cxa2076q Datasheet - Page 40

• Manufacturer Part Number: cxa2076q
• Description: Y/c/rgb/d For Pal/ntsc Color Tvs
• Manufacturer: Sony Electronics

CXA2076Q
3. Signal processing
The CXA2076Q is comprised of sync signal processing, H deflection signal processing, V deflection signal
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processing, and Y/C/RGB signal processing blocks, all of which are controlled by the I
C bus.
1) Sync signal processing
Pin 48 (SYNC OUT) outputs at 2Vp-p either the internal signal (CVIN/YIN) selected by the internal video
switch, or the external sync signal input from Pin 56 (EXT SYNC IN).
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This selection is controlled by the I
C bus. The signal output from Pin 48 is buffered by a PNP Tr. and is then
input to HSIN (Pin 47) or VSIN (Pin 46) through a suitable filter.
The Y signals input to Pins 46 and 47 are sync separated by the horizontal and vertical sync separation
circuits. The resulting horizontal sync signal and the signal (FH = 15625Hz or 15734Hz) obtained by frequency
dividing the 32FH-VCO output using the ceramic oscillator (frequency 500kHz or 503.5kHz) by 32 are phase-
compared, the AFC loop is constructed, and an H pulse synchronized with the H sync is generated inside the
IC. Adjustment of the H oscillator frequency is unnecessary. When the AFC is locked to the H sync, 1 is output
to the status register (HLOCK) and that can be used to detect the presence of the video signal.
The vertical sync signal is sent to the V countdown block where the most appropriate window processing is
performed to obtain V sync timing information which resets the counter. AKB and other V cycle timing are then
generated from this reset timing.
2) H deflection signal processing
The H pulse obtained through sync processing is phase-compared with the H deflection pulse input from Pin
38 to control the phase of the HDRIVE output and the horizontal position of the image projected on the CRT.
In addition, the compensation signal generated from the V sawtooth wave is superimposed, and the vertical
picture distortion is compensated.
The H deflection pulse is used for H blanking of the video signal. When the pulse input from Pin 38 has a
narrow width, the pulse generated by the IC can be added to the H deflection pulse and used as the H
blanking pulse (HBLKSW).
Pin 38 is normally pulse input, but if the pin voltage drops to the GND level, HDRIVE output stops and 1 is
output to the status register (XRAY). To release this status, turn the power off and then on again.
3) V deflection signal processing
The V sawtooth wave is generated at the cycle of the reset pulse output from the countdown system. After
performing wide deflection processing for this sawtooth wave, picture distortion adjustment is performed by the
VDRIVE and E/WDRIVE function circuits and the signal is output as the VDRIVE and E/WDRIVE signals.
4) Y signal processing
Either CVIN, input from Pin 53, or YIN, output from Pin 55, is selected by the video switch and then is passed
to the Y signal processing circuit as the Y signal. The input level is 1Vp-p.
The Y signal passes through the subcontrast control, the trap for eliminating the chroma signal, the delay line,
the sharpness control, the clamp and the black expansion circuits, and is then output to Pin 5 as YOUT. The
differentiated waveform of the Y signal, advanced for about 200ns from YOUT is output from Pin 49 as the VM
signal. The delay time is set by the bus register (DL).
When CVIN is selected, the trap is on; when YIN is selected, the trap is off.
The f0 of the internal filter is automatically adjusted within the IC. Because the f0 of the filter is not specified
when the color killer function is operating, turn the trap off if there are any difficulties. In addition, the f0 of the
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trap will be affected slightly by variations among IC, so fine adjustment through the I
C bus (TRAP-F0) may be
required.
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