cxd1196ar Sony Electronics, cxd1196ar Datasheet
cxd1196ar
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cxd1196ar Summary of contents
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... CD-ROM DECODER For the availability of this product, please contact the sales office. Description The CXD1196AR is a CD-ROM decoder LSI with a built-in ADPCM decoder. Features • CD-ROM, CD-I and CD-ROM XA format compatible • Real time error correction • Double speed playback compatible (when V =5.0± ...
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... XMOE XMWR MDBO-MDB7 3 4 24-31 5-11.13-20 DMA FIFO DMA SEQUENCER PRIORITY RESOLVER DESCRAMBLER SYNC CONTROL ADPCM ECC DECODER CORRECTOR DIGITAL FILTER 57 2.12.23.32.42.52.63.72 33.73 35 GND V EMP DD —2— CXD1196AR 69 DO- XRD CPU I/F 65 XWR 66 XCS 68 AO INT 67 44 INTP 51 DRO CPU DMA 53 XDAC 45 WCKO 46 LRCO DAC ...
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... Buffer memory data bus (MSB) Ground pin Power supply pin C2 pointer positive logic signal from CD player Emphasis positive logic signal from CD player Bit clock signal from CD player Data signal from CD player LR clock signal from CD player Test pin Test pin —3— CXD1196AR ...
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... CPU data bus 72 GND — Ground pin 73 V — Power supply pin CPU data bus CPU data bus CPU data bus CPU data bus CPU data bus (LSB) 79 TA0 I Test pin — Description —4— CXD1196AR ...
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... V IH4 DD V IL4 500 =–3 mA 0.5 V OH2 OL2 OL —5— CXD1196AR =0 V, Topr=– °C) SS Typ. Max. Unit 0 0.6 V –100 –240 µA 100 240 µA – ...
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... V 0.7 V IH4 DD V IL4 1 =–1.3 mA 0.5 V OH2 =1.3 mA OL2 OL —6— CXD1196AR =0 V, Topr=– °C) SS Typ. Max. Unit 0 0.5 V –25 –60 µ µA –50 – ...
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... All output pins except XTL2 9. All input pins except 7 10. input : XTL1, output : XTL2 Input/Output Capacitance Item Input pin Output pin Input/Output pin Symbol Min. Typ OUT C OUT —7— CXD1196AR ( f=1 MHz Max. Unit ...
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... Trr1 150 (250) Twwl Thaw Tsdw Thdw Symbol Min. Tsaw 30 (70) Thaw 20 (50) Tsdw 50 (70) Thwd 20 (30) Twwl 70 (100) —8— CXD1196AR =0 V, Topr=– °C, and Typ. Max. Unit ns ns 120 (200 (40 Typ. Max. Unit ...
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... Data float time (with respect to XRD ) L level XRD pulse width Trrl Thac Tdrd Tfrd Symbol Min. Tdar1 Tdar2 Tsac 10 (30) Thac 10 (30) Tdrd Tfrd 0 Trrl 150 (250) —9— CXD1196AR Tdar2 Typ. Max. Unit 50 (120 (120 120 (200 (40 ...
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... Note that XSLOW is bit 7 of DRVIF register. When XSLOW = ‘H’ , make sure that the CXD1196AR is connected to an SRAM with an access time of less than 120 ns. When XSLOW = ‘L’ , make sure that the CXD1196AR is connected to an SRAM with an access time of less than 320 ns. Toel ...
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... LRCK, C2PO setting time (with respect to BCLK) LRCK, C2PO holding time (with respect to BCLK) Tbck Tbck Tsb1 Thb1 Thb2 Tbck Tbck Tsb1 Thb1 Thb2 Symbol Min. Fbck Tbck 85 Tsb1 50 Thb1 50 Tsb2 50 Thb2 50 —11— CXD1196AR Tsb2 Thb2 Typ. Max. Unit 5.7 MHz ...
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... BCKO frequency BCKO pulse width DATO, WCKO, LRCO setting time (with respect to BCKO ) DATO, WCKO, LRCO holding time (with respect to BCKO ) Tbco Tbco Tsbo Thbo Thbc Symbol Min. Fbco Tbco 50 Tsbo 30 Thbo 30 —12— CXD1196AR Tsbo Typ. Max. Unit 8.4672 MHz ...
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... Symbol Min. Fmax 16.9344 Tw Twlx Tf Symbol Min. Twhx 20 Twlx 20 Tw Vihx V –1.0 DD Vilx Tr Tf —13— CXD1196AR Typ. Max. Unit MHz Vihx Vihx 0 Vihx 0.1 Vilx Typ. Max. Unit 0 ...
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... MA0-14 (BUFFER MEMORY ADDRESS : OUT) Address signals to buffer memory (4) MDB0-7 (BUFFER MEMORY DATA BUS : BUS) Buffer memory data bus signal pulled typical 25 k resistor In an ADPCM decode playback drive, make sure that the CXD1196AR is connected to a 256 Kbit ( Kbyte) SRAM w 1 ...
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... These pins are normally kept in the opened state. (1) TD0-7 (Input/Output) : Data bus for IC test. Pulled typical 25 k resistor. (2) TDIO (Input) : Input pin for IC test. Pulled typical 50 k resistor. (3) TA0-3 (Input) : Input pins for IC test. Pulled typical 50 k resistor. —15— CXD1196AR ...
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... CXD1196AR ...
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... To output 8.4672 MHz clock from CLK pin output The values of the individual bits of this register must be changed with the decoder in the disabled state. Table 2.1.1 shows the values of bits of bit 6 through set when the CXD1196AR is connected to Sony DSPs for CD. Fig. 2.2.1 (1) through (3) show input timing charts. ...
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... When this bit is set at ‘H’, the CXD1196AR is internally initialized. The bit setting will automatically change to ‘L’ when the internal initialization of the CXD1196AR is completed. Therefore, there is no need for the CPU to change the setting at ‘L’. Initialization of the CXD1196AR will be completed in 500ns after the bit has been set at ‘H’ by the CPU. ...
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... Interrupt Mask (INTMSK) Register When the individual bits of this register are set at ‘H’, an interrupt request from the CXD1196AR to the CPU is enabled in response to the corresponding interrupt status. (That is, when the interrupt status is created, the INT pin is made active.) The value of the individual bits of the register does not affect the corresponding interrupt status ...
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... Each time data to be sent to the CPU is read from the buffer, the DMAADRC is incremented. The CPU sets the head address of DMA in the DMAADRC before starting DMA. The CPU can read and set the contents of the DMAADRC at any time. Do not change the contents of the DMAADRC during execution of DMA. —20— CXD1196AR ...
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... Before execution of the write only mode and real time correction mode of the DECODER, the CPU sets the buffer write head address in the DRVADRC. The CPU can read and set the contents of DRVADRC at any time. During execution of DMA, do not change the contents of DRVADRC. —21— CXD1196AR ...
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... CXD1196AR ...
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... Indicates the Sync Mark interval was less than 2351 bytes. On this sector, neither ECC nor EDC is executed. Bit0 NOSYNC Indicates that the SYNC Mark, not detected in the predetermined position, is one internally inserted. 2.2.5 Header Flag (HDRFLG) Register Indicates the value of the error pointer of the Header and Sub Header registers. —23— CXD1196AR ...
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... Bit0 M/S (MONO/STEREO) This bit indicates “monaural” or “stereo” of ADPCM playback coding information. ‘H’ : Stereo ‘L’ : Monaural CMODE ‘X’ ‘L’ MODE1 ‘L’ ‘H’ MODE2, FORM1 ‘H’ ‘H’ MODE2, FORM2 —24— CXD1196AR ...
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... EN bit6 bit5 bit4 bit3 bit14 bit13 bit12 bit11 Write Registers —25— CXD1196AR bit2 bit1 bit0 RA0 RA2 RA1 BCK LSB CLKL MD0 1st SW RPS ADP OPEN TART EN DEC DEC DEC MD2 ...
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... Read Registers —26— CXD1196AR bit2 bit1 bit0 RA2 RA1 RA0 bit2 bit1 bit0 ECC SHRT NO OK SCT SYNC CHAN SUB CI NEL ...
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... CXD2500 is in 64-bit slot mode; CXD2500 CXD1196A DA12 38 38 LRCK DA14 36 37 DATA 37 36 BCLK DA13 DRVIF register : LHLHXH 32K Byte SRAM 3 4 5-11 13-20 24-31 CXD1196AR 69-71 74-78 CPU CXD1196AR Connection Diagram —27— CXD1196AR D/A CONVERTER WCKO 45 LRCO 46 DATO 47 BCKO 48 MUTE 50 59 XRST V , GND pins excluded. DD ...
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... LQFP (PLASTIC) 14.0 ± 0.2 12.0 ± 0 (0.22 0.08 0.18 – 0.03 0. 0.2 1.5 – 0.1 NOTE: Dimension “ ” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LQFP-80P-L01 LQFP080-P-1212 LEAD MATERIAL PACKAGE MASS —28— CXD1196AR + 0.05 0.127 – 0.02 0.1 EPOXY RESIN SOLDER PLATING 42 ALLOY 0.5g ...