74HCT14DR2G ON Semiconductor, 74HCT14DR2G Datasheet
74HCT14DR2G
Specifications of 74HCT14DR2G
Related parts for 74HCT14DR2G
74HCT14DR2G Summary of contents
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Hex Schmitt−Trigger Inverter with LSTTL Compatible Inputs High−Performance Silicon−Gate CMOS The 74HCT14 may be used as a level converter for interfacing TTL or NMOS outputs to high−speed CMOS inputs. The HCT14 is useful to “square up” slow input rise ...
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... GND 7 8 FUNCTION TABLE Input Output ORDERING INFORMATION Device 74HCT14DR2G 74HCT14DTR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. LOGIC DIAGRAM Package SOIC−14 (Pb− ...
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... Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tested to EIA/JESD22−A114−A. 2. Tested to EIA/JESD22−A115−A. 3. Tested to EIA/JESD78. 4. For high frequency or heavy load considerations, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol V DC Supply Voltage ...
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... TLH t Transition Time, Any C THL Output 8. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D). C Power Dissipation Capacitance, per Inverter (Note Used to determine the no−load dynamic power consumption: P Semiconductor High− ...
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INPUT A 2.7 V 1 PLH 90% 1.3 V OUTPUT Y 10 TLH THL Figure 1. Switching Waveforms TEST POINT OUTPUT DEVICE UNDER TEST *Includes all probe and jig capacitance. Figure 2. ...
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... G −T− SEATING 14 PL PLANE 0.25 (0.010 14X 0.58 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE 0.25 (0.010 ...
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... S A −V− C 0.10 (0.004) −T− SEATING G D PLANE 14X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE 0.25 (0.010) ...
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... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...