SL15101 SPECTRALINEAR [SpectraLinear Inc], SL15101 Datasheet
SL15101
Related parts for SL15101
SL15101 Summary of contents
Page 1
... output clock frequencies, Spread %, output rise and fall times, crystal load, modulation frequency and PD#/OE/SSON#/FS functions can be programmed to meet the needs of wide range of applications. The SL15101 operates from 2.5V to 3.3V power supply voltage range. The product is offered in 8-pin TSSOP package with commercial and industrial grades. ...
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... FS control pin. Programmable SSON# or Frequency Select (FS) Control pin. If SSCG# function is programmed: Spread-on=0(Low) or Spread-off=1(High function is programmed: The clock frequencies can be switched between two sets of frequencies as programmed. If SSON programmed, the pin weakly pulled low to VSS. SL15101 Page ...
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... The set of frequencies in Table 1 is given as en example, using 48MHz crystal. The SL15101 also allows a fan-out meaning that Pins and 8 can be programmed to the same frequencies with or without spread. ...
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... IIH PD#, OE, SSON and no pull-up/down resister used VIN=GND, Pins 4 and 8. If outputs are programmed as IIL PD#, OE, SSON and no pull-up/down resister used CMOS Level, if Pins 4 and 8 RPU/D programmed as PD#, OE, SSON SL15101 Min Max Unit -0.5 4.6 -0.5 VDD+0 °C -40 85 ° ...
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... CL=15pF 80% of VDD Programmable, VDD=3.3V, CL=15pF 80% of VDD Programmable, VDD=3.3V, CL=15pF 80% of VDD Programmable, VDD=3.3V, CL=15pF 80% of VDD Programmable, VDD=3.3V, CL=15pF 80% of VDD Programmable, VDD=3.3V, CL=15pF 80% of VDD Programmable, VDD=3.3V, CL=15pF 80% of VDD SL15101 - 7 ...
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... SSCLK/REFCLK VIN=VDD, Pins 4 and 8. If outputs are programmed as IIH PD#, OE, SSON and no pull-up/down resister used VIN=GND, Pins 4 and 8. If outputs are programmed as IIL PD#, OE, SSON and no pull-up/down resister used SL15101 - 235 290 - 185 245 - 150 350 - 3.5 5 ...
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... REFCLK, clock input SSCLK REFCLK, Xtal input REFCLK, clock input Clock Input, Pin 3 Programmable, VDD=2.5 CL=15pF 80% of VDD Programmable, VDD=2.5 CL=15pF 80% of VDD Programmable, VDD=2.5 CL=15pF 80% of VDD Programmable, VDD=2.5 CL=15pF 80% of VDD SL15101 90 160 230 - 7.0 8 -10 - ...
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... VDD+/-10% CMOS Level, if Pins 4 and 8 VIL programmed as PD#, OE, SSON CMOS Level, if Pins 4 and 8 VIH programmed as PD#, OE, SSON# or FS. IOH=10mA , If Pins and VOH1 8 are programmed as SSCLK/REFCLK IOL=10mA, If Pins and 8 VOL1 are programmed as SSCLK/REFCLK SL15101 - 1.10 1.35 - 0.90 1.10 - 0.70 0.85 - 260 310 - 210 250 - 150 ...
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... Pins and programmed as SSCLK or REFCLK Condition Crystal or Ceramic Resonator External Clock SSCLK REFCLK, crystal or resonator input REFCLK, clock input SSCLK REFCLK, Xtal input REFCLK, clock input Clock Input, Pin 3 Programmable, VDD=3.3V, CL=15pF 80% of VDD SL15101 - - 100 160 220 - 8.2 9 ...
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... Time from OE falling edge to Hi-Z at outputs (Asynchronous) Center Spread, SSCLK-1/2/3/4 Down Spread, SSCLK-1/2/3/4 Variation of programmed Spread % Programmable, 31.5 kHz standard Condition VDD VDD+/-10% CMOS Level, if Pins 4 and 8 VIL programmed as PD#, OE, SSON CMOS Level, if Pins 4 and 8 VIH programmed as PD#, OE, SSON# or FS. SL15101 - 2.00 2.40 - 1.40 1.70 - 1.10 1.35 - 0.85 1.00 - 0.70 0.85 - ...
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... Maximum setting value PCout Resolution (programming steps) Pins 4 and 8 CIN2 If programmed as PD#, OE, SSON or FS Pins and programmed as SSCLK or REFCLK Condition Crystal or Ceramic Resonator External Clock SSCLK REFCLK, crystal or resonator input REFCLK, clock input SSCLK SL15101 VDD-0 0 160 230 - 7.2 8 ...
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... Time from PD# rising edge to valid frequency at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) Center Spread, SSCLK-1/2/3/4 Down Spread, SSCLK-1/2/3/4 Variation of programmed Spread % Programmable, 31.5 kHz standard SL15101 4.80 5. ...
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... Refer to the Table 5 for the recommended crystal specifications. Rev 1.8, August 10, 2007 0.1 F VDD(1) XIN(3) SSCLK1(6) 66 MHz, +/-1.5% Spread SSCLK2(7) 66 MHz, +/-1.5% Spread XOUT(2) SSCLK3(4) 33 MHz, +/-1.5% Spread REFCLK(8) 27 MHz, No Spread SL15101 VSS(5) PCin(pF) =PCout(pF)= [(CL(pF) – Cp(pF)/2 SL15101 VDD resistor as close to the Page ...
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... SL15101 Comments Fundamental Mode – AT Cut Load for +/-0 ppm Fo resonance value F-Range: 8.0 to 12.999 MHz F-Range: 13.0 to 19.999 MHz F-Range: 20.0 to 48.000 MHz F-Range: 8.0 to 19.999 MHz F-Range: 20.0 to 48.000 MHz SMD Xtals Through Hole (Leaded) Xtals Page ...
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... Package Outline and Package Dimensions 8-Pin TSSOP Package (173 Mil) Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Rev 1.8, August 10, 2007 Condition Still air JA 1m/s air flow JA 3m/s air flow JA Independent of air flow JC SL15101 Min Typ Max Unit - 110 - °C/W - 100 - °C °C ° ...
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... SL15101ZC-XXX SL15101ZC-XXX SL15101ZCT-XXX SL15101ZC-XXX SL15101ZI-XXX SL15101ZI-XXX SL15101ZIT-XXX SL15101ZI-XXX Notes: 1. All SLI products are RoHS compliant. 2. “XXX” is “Dash” number and will be assigned by SLI for final programmed samples or production units based on the each customer programming requirements. While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use ...