SL15101 SPECTRALINEAR [SpectraLinear Inc], SL15101 Datasheet - Page 13

• Manufacturer Part Number: SL15101
• Description: Programmable Spread Spectrum Clock Generator (SSCG)
• Manufacturer: SPECTRALINEAR [SpectraLinear Inc]

External Components & Design Considerations
Typical Application Schematic
Rev 1.8, August 10, 2007
Comments and Recommendations
Decoupling Capacitor: A decoupling capacitor of 0.1 F must be used between VDD and VSS on the pins 1 and 5.
Place the capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the
VDD pin and to the GND via should be kept as short as possible Do not use vias between the decoupling capacitor
and the VDD pin.
Series Termination Resistor: A series termination resistor is recommended if the distance between the outputs
(SSCLK or REFCLK pins) and the load is over 1 ½ inch. The nominal impedance of the SSCLK output is about 30 .
Use 20
SSCLK output as possible.
Crystal and Crystal Load: Use only parallel resonant fundamental crystals. DO NOT USE higher overtone crystals.
To meet the crystal initial accuracy specification (in ppm); the internal on-chip programmable capacitors PCin and
PCout must be programmed to match the crystal load requirement. These values are given by the formula below:
Where CL is crystal load capacitor as given by the crystal datasheet and Cp(pF) is the compensation factor for the
total parasitic capacitance at XIN or XOUT pin including PCB related parasitic capacitance.
As an example; if a crystal with CL=18pF is used and Cp=4pF, by using the above formula, PCin=PCout=[(18-(4/2)] x
2 = 32pF. Programming PCin and PCout to 32pF assures that this crystal sees an equivalent load of 18pF and no
other external crystal load capacitor is needed. Deviating from the crystal load specification could cause an increase
in frequency accuracy in ppm. Refer to the Table 5 for the recommended crystal specifications.
resistor in series with the output to terminate 50 trace impedance and place 20
27MHz
XOUT(2)
XIN(3)
PCin(pF) =PCout(pF)= [(CL(pF) – Cp(pF)/2)] x 2
SL15101
VDD(1)
VSS(5)
REFCLK(8)
SSCLK1(6)
SSCLK2(7)
SSCLK3(4)
0.1 F
66 MHz, +/-1.5% Spread
66 MHz, +/-1.5% Spread
33 MHz, +/-1.5% Spread
27 MHz, No Spread
VDD
resistor as close to the
SL15101
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