ATS75D8 ETC2 [List of Unclassifed Manufacturers], ATS75D8 Datasheet - Page 9

• Manufacturer Part Number: ATS75D8
• Description: LOW- OLTAGE 2-WIRE DIGITAL TEMPERATURE SENSOR With Thermal Alarm
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Serial Data Bus Operation
General Operation
Writing to and reading from the aTS75 registers is
accomplished via the SMBus-compatible two-wire serial
interface. SMBus protocol requires that one device on the
bus initiates and controls all read and write operations.
This device is called the “master” device.
device also generates the SCL signal which is the clock
signal for all other devices on the bus. All other devices on
the bus are called “slave” devices. The aTS75 is a slave
device.
receive data on the bus.
During SMBus operations, one data bit is transmitted per
clock cycle. All SMBus operations follow a repeating nine
clock-cycle pattern that consists of eight bits (one byte) of
transmitted data followed by an acknowledge (ACK) or not
acknowledge (NACK) from the receiving device. Note that
there are no unused clock cycles during any operation—
therefore there must be no breaks in the stream of data
and ACKs/NACKs during data transfers. Conversely having
too few clock cycles can lead to incorrect operation if an
inadvertent 8-bit read from a 16-bit register occurs.
For most operations, SMBus protocol requires the SDA line
to remain stable (unmoving) whenever SCL is high—i.e.,
transitions on the SDA line can only occur when SCL is
low.
device issues a start or stop condition. Note that the slave
device cannot issue a start or stop condition.
The following are definitions for some general SMBus
terms:
Start Condition: This condition occurs when the SDA line
transitions from high to low while SCL is high. The master
device uses this condition to indicate that a data transfer is
about to begin.
Stop Condition: This condition occurs when the SDA line
transitions from low to high while SCL is high. The master
device uses this condition to signal the end of a data
transfer.
Acknowledge and Not Acknowledge:
transferred
acknowledge(ACK) after receiving each byte of data. A
master device sends an acknowledge(ACK) following only
the first byte read from a 2-byte register. The receiving
device sends an ACK by pulling SDA low for one clock.
Following the last byte, a master device sends a "not
acknowledge"(NACK) followed by a stop condition. A
NACK is indicated by leaving SDA high during the clock
after the last byte.
© Andigilog, Inc. 2005
The exceptions to this rule are when the master
Both the master and slave devices can send and
to
the
slave
device
When data is
sends
The master
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an
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Slave Address
Each slave device on the bus has a unique 7-bit address
so the master can identify which device is being read from
or written to.
The aTS75 address is as follows:
The four MSBs of the aTS75 address are hardwired to
1001. The three LSBs are user configurable by tying the
A0, A1 and A2 pins to either V
eight different aTS75 addresses, which allows up to eight
aTS75s to be connected to the same bus.
Writing To and Reading From the aTS75
All read and write operations must begin with a start
condition generated by the master device. After the start
condition, the master device must immediately send a
slave address (7 bits) followed by a read/write bit. If the
slave address matches the address of the aTS75, the
aTS75 sends an ACK after receiving the read/write bit by
pulling the SDA line low for one clock. See Figure 8 –
Figure 13 for timing diagrams for all aTS75 operations.
Setting the Pointer
For all operations the pointer stored in the Command
Register must be pointing to the register (Temperature,
Configuration, T
read from. To change the pointer value in the Command
Register, the read/write bit following the address must be 0.
This indicates that the master will now write new
information into the Command Register.
After the aTS75 sends an ACK in response to receiving the
address and read/write bit, the master device must transmit
an appropriate 8-bit pointer value as explained in the
Registers section of this data sheet.
an ACK after receiving the new pointer data.
The pointer set operation is illustrated in Figure 8. Anytime
a pointer set is performed, it must be immediately followed
by a read or write operation. Note that the 6 MSBs of the
pointer value must be zero. If the 6 MSBs are not zero, the
aTS75 will not send an ACK and will internally terminate
the operation.
retains the current pointer value between operations.
Therefore, once a register is being pointed to, subsequent
read operations do not require a pointer set cycle.
1
OS
Also recall that the Command Register
0
or T
HYST
0
) that is going to be written to or
1
DD
A2
or GND.
April 2006 - 70A03204
The aTS75 will send
A1
A0
This provides
aTS75