cxd2408r Sony Electronics, cxd2408r Datasheet
cxd2408r
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cxd2408r Summary of contents
Page 1
... Timing Generator for Progressive Scan CCD Image Sensor For the availability of this product, please contact the sales office. Description The CXD2408R developed to generate the timing pulses required by the Progressive Scan CCD image sensors as well as signal processing circuits. Features • EIA support • ...
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... XVHOLD 24.5MHz OUTPUT CONTROL TG H-DECODER 1/390 COUNTER DECODE GATE – 2 – CXD2408R VRI 62 HRI V-CONTROL V-DECODER 1/525 20 TEST1 21 TEST2 31 TEST3 32 TEST4 48 TEST8 TEST7 35 TEST CIRCUIT TEST6 34 TEST5 33 52 ...
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... SYNC 57 HDI 58 VDI 59 HDO 60 VDO 61 HRI 62 VRI 63 CKI CXD2408R (G/ – 3 – CXD2408R TEST4 TEST3 31 30 XRS XSHD 29 28 XSHP 27 XSG XV1 26 25 XV2 ...
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... XSHD O Data sample-and-hold pulse. 30 XRS O Sample-and-hold pulse. 31 TEST3 O Test output. Normally open. 32 TEST4 O Test output. Normally open. 33 TEST5 O Test output. Normally open. 34 TEST6 O Test output. Normally open. 35 TEST7 I Test input. Set at Low in normal operation. (With pull-down resistor) Description – 4 – CXD2408R ...
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... Composite sync output. 58 HDI I Horizontal sync signal input. 59 VDI I Vertical sync signal input. 60 HDO O Horizontal sync signal output. 61 VDO O Vertical sync signal output. 62 HRI I Horizontal reset signal input. 63 VRI I Vertical reset signal input. 64 CKI I 2 fck clock input. Description – 5 – CXD2408R ...
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... ICX074AL in normal DD operating state ( 0V Symbol Min. Typ. Max. C — — — — 11 OUT – 6 – CXD2408R = 4.75 to 5.25V, Topr = –20 to +75°C) Min. Typ. Max. Unit 4.75 5.0 5. –0.8 V 0.4 V –0 – ...
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... CLD rising delay, activated by the falling edge of CK tpd2 0.7V DD 0.3V DD tpd3 tpd4 0.7V DD tpd6 tpd5 tpd8 tpd7 0.7V DD 0.3V DD tpd9 0.3V DD tpd12 0.7V DD tpd14 tpd13 0.7V DD Definition – 7 – CXD2408R 0.7V DD tpd10 0.7V DD Typ. Unit ...
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... 5.0V, Topr = 25°C, Load capacity of XH1 = 10pF, Load capacity 10pF) DD Symbol t rH1 XH1 rise time t fH1 XH1 fall time t rRG RG rise time t fRG RG fall time 0.9V DD 0.1V DD tfH1 trH1 DD trRG tfRG Definition – 8 – CXD2408R Typ. Unit ...
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... VDO 2 Symbol t p1 Range of resetting to ODD t p2 Range of resetting to EVEN t p3 Range of resetting to ODD t p4 Prohibited area t p5 Prohibited area 2 tp3 f L: ODD H: EVEN H tp5 259H 259H Definition – 9 – CXD2408R ODD EVEN Specified value Unit 21.9 µs 31.6 µs 9.7 µs 200 ns 200 ns ...
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... Range of resetting to ODD t p4 Prohibited area t p5 Prohibited area In the direct reset mode, the cycle of HD can be arbitrary. Therefore, tp3 is not specified. 2 tp3 f L: ODD H: EVEN H tp5 Definition – 10 – CXD2408R ODD EVEN Specified value Unit 21.9 µs 31.6 µs — µs 200 ns 200 ns ...
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... Direct reset HV reset L H External synchronization Internal synchronization L Normal Normal operation operation Direct reset reset reset – 11 – CXD2408R Remarks Electronic shutter speed input method H 1/60s interlaced L H External synchronization H Random trigger Normal operation shutter L H Normal Direct reset reset ...
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... – 12 – CXD2408R Shutter speed Shutter off 1/100 (s) 1/60 (s) 1/125 (s) 1/250 (s) 1/500 (s) 1/1000 (s) 1/2000 (s) 1/4000 (s) 1/10000 (s) 2FLD 4FLD 6FLD 8FLD 10FLD 12FLD 14FLD 16FLD ...
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... ED0 rising set-up time, activated by the rising edge of ED1 t w1 ED1 pulse width (serial input ts2 th2 tw1 ts1 ts0 tw0 Definition – 13 – CXD2408R SMD1 SMD2 Dummy Min. Max. 20ns — 20ns — 20ns — 20ns 50µs 20ns — 20ns — ...
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... In case of starting with serial input setting (PS = H), be sure to transfer shutter speed data in the range of specification after power is turned on, and then use it.. = Load value) 16 1/10169 1/4435 1/2085 1/1012 1/499 1/252 1/125 1/100 or less cannot be used . – 14 – CXD2408R ...
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... In the random trigger shutter mode, V-direction functions of a sync signal generator are halted result, sync signals VD and FLD are also halted. TRIG HD XSG XSUB XV1 XV2 XV3 WEN HD reset XSUB reset Shutter speed – 15 – CXD2408R ...
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... Resetting is done to synchronize a plural number of camera systems whose clock frequencies are the same. There are two reset inputs: HRI and VRI. When their falling edge is detected, resetting is carried out. The CXD2408R has two reset modes: normal reset and direct reset. Details of the reset modes are described in the following pages. ...
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... Resetting is done for ODD or EVEN field, depending on the input timing of the V reset signal. The identification timing is shown in Electrical Characteristics (Field identification). FIELD.E HRI HDO VRI 9H VDO FIELD.O HRI HDO VRI 9H VDO H reset HRI HD OUT FIELD.O 259H FIELD.E 259H 57.1 to 57.2µs (701 to 702 bit) Reset – 17 – CXD2408R 6.3 to 6.37µs ...
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... The minimum HRI reset pulse width is 0.3µs. Resetting is done for ODD or EVEN field, depending on the input timing of the V reset signal. The identification timing is shown in Electrical Characteristics (Field identification). 5-2-1. V reset FIELD.E HRI HDO VRI VDO FIELD.O HRI HDO VRI VDO FIELD.O 9H FIELD.E 9H – 18 – CXD2408R ...
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... HV reset (1/60s interlaced readout mode) FIELD.E HDO HRI VDO VRI XSG ID FIELD.O HDO HRI VDO VRI XSG ID CL HRI HDO FIELD.O 9H FIELD.E 9H – 19 – CXD2408R ...
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... HV reset (1/30s non-interlaced readout mode) HDO HRI VDO VRI XSG ID HDO HRI VDO VRI XSG ID CL HRI HDO 9H 9H – 20 – CXD2408R ...
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... Timing Chart (1) <Vertical direction> 1/60s interlaced readout (RM = High) FLD VDO BLK HDO XV1 XV2 XV3 OUT1 OUT2 XSG XVHOLD XVOG XHHG1A XHHG1B XHHG2 PBLK XCPOB XCPDM ID WEN – 21 – CXD2408R ...
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... Timing Chart (2) <Vertical direction> 1/30s non-interlaced readout (RM = Low) FLD VDO BLK HDO XV1 XV2 XV3 OUT1 XSG XVHOLD XVOG XHHG1A XHHG1B XHHG2 PBLK XCPOB XCPDM ID WEN – 22 – CXD2408R ...
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... CXD2408R ...
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... CXD2408R ...
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... XV2 XV3 XSG Timing Chart (6) <V2/V3 simultaneous readout timing> 1/30s non-interlaced (RM = Low) HD 42.4µs (520 bits) ODD Field XV1 XV2 XV3 XSG 2.53µs (31 bits) 2.53µs (31 bits) 16.1µs (198 bits) 2.53µs (31 bits) 2.53µs (31 bits) 16.1µs (198 bits) – 25 – CXD2408R 2.94µs (36 bits) 2.94µs (36 bits) ...
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... Timing Chart (7) <High-speed phase> HD CKI CL XH1 XH2 RG XSHP XSHD XRS CLD – 26 – CXD2408R ...
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... Timing Chart (8) <SG vertical direction> Field E HDO VDO SYNC BLK FLD Field O HDO VDO SYNC BLK FLD O : ODD E : EVEN Field O 9H 20H Field E 9H 20H – 27 – CXD2408R ...
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... FLD 11.82µs (145 bits) 2FH 9.86µs (121 bits) 9.78µs (120 bits) FH 22.00µs (27 bits) 6.36µs (78 bits) 10.76µs (132 bits) 4.89µs (60 bits) 2.45µs (30 bits) 4.89µs (60 bits) 26.89µs (330 bits) ODD EVEN 10.14µs (124 bits) 63.56µs (780 bits) 1/2H 31.78µs (390 bits) – 28 – CXD2408R ...
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... CXD2408R ...
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... EIAJ CODE LQFP064-P-1010 JEDEC CODE 64PIN LQFP (PLASTIC (0.22 0.08 0.127 – 0.02 + 0.2 1.5 – 0.1 NOTE: Dimension “ ” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS – 30 – CXD2408R + 0.05 0.1 EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.3g ...