cxd2832er Sony Electronics, cxd2832er Datasheet
cxd2832er
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cxd2832er Summary of contents
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... Zero-IF Tuner IC for Digital Satellite Broadcast Description The CXD2832ER developed for direct orthogonal detection of 1st IF signal ( GHz) from RF converter block in a digital satellite broadcast receiver system. The CXD2832ER incorporates all the functions (LNA RF gain control amplifier, oscillator circuit, and other RF circuits, a baseband LPF, baseband gain control amplifier, tuning PLL) required for a satellite broadcast tuner ...
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Basic Specifications Receiving frequency range Input level range (Embedded LNA active) Power supply voltage Standard baseband output level Tuning frequency step (PLL comparison frequency) Baseband bandwidth Clock frequency 950 to 2150 MHz –85 to –10 dBm 2.5/3.3 V 0.7 Vp-p ...
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... Gain control amplifier for baseband signal Buffer Output buffer circuit for baseband signal VGA control IQ Mixer RF VGA Buffer VGA LPF IQ Generator 1/2 PLL Prescaler Reference OSC CXD2832ER VREF18 LNA 13 RFIN 12 RFGND 11 TEST 10 POWER_SAVE Driver 1/1 1/2 9 VCOGND VCO 8 VCOREG 1 ...
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Pin Description and Input/Output Pin Equivalent Circuit (Pin voltage shows typical DC voltage value when AGCI = 0 V) Pin Symbol No voltage [V] 1 GPIO 2 DGND XTO 3, 4 XTI 5 PLLREG ...
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... Test pin 11 No connect 10 kΩ 12 RFGND GND for RF circuits AV RFREG Input for RF signal 13 12 RFGND AV AREG Connecting capacitor for internal 1 kΩ reference voltage. 14 Please connect GND via capacitor of 1 F or more. 9 kΩ 18 AGND - 5 - CXD2832ER Description ...
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... AGND - 6 - CXD2832ER Description External capacitor connection pin for regulator of RF circuit. Please connect GND via capacitor of 1 F or more. External capacitor connection pin for regulator of base band circuit. Please connect GND via capacitor of 1 F or more. ...
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Pin Pin Symbol No voltage [V] 24 RSTX — 25 SCL — 26 SDA — 27 ADSL 0 to 2.2 28 REFOUT — Equivalent circuit 500 Ω 24 Negative logic hardware reset pin Hardware reset is necessary when power up. ...
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... REFOUT 28 REF 2 Ω OUT NM 27 ADSL SDA 26 220 Ω SCL 220 Ω RSTX 1000 pF 23 IOUTN 1 µF 2.2 kΩ IOUTP 22 1 µ µF 2.2 kΩ 1 µF 2.5 V GND IOUT QOUT CXD2832ER SDA SCL RSTX IOUTN IOUTP QOUTP QOUTN ...
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... LNA is disabled DD VIH VIL VOL1 Sink current VPH Source current VPL Sink current IGD Source/Sink current VIAH ILAH AGCIN = 3.3 V ILRH ILPH Input voltage = 3 CXD2832ER Min. Typ. Max. Unit 125 105 ...
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... Same measurement condition as IIP2L Local OSC leak to RFIN Attenuation at LPF setting value (fc) Attenuation at twice frequency of LPF setting. 1 k loaded When using as external input (under When using as external input (under CXD2832ER Min. Typ. Max. Unit –85 –10 dBm –75 0 dBm 1.5 Vp-pd 1 Vp-p – ...
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Electrical Characteristics (Logic block) (Circuit voltage = 2 Item SCL clock frequency Start - Hold time Stop - Setup time Bus free time between “STOP” condition and “START” condition Data - Setup time High hold ...
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Power-on sequence The sequence from power-on to hardware reset is below. Set RSTX low level for more than more after stability time of the crystal oscillation problem which AV DD The communication of ...
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... Buffer: This output circuit outputs the baseband signal to a demodulator IC. It can be used as a single output IC by termination one side of the differential outputs by the recommended registor and capacitor. MIXER RFVGA LPF VGA 90 deg PLL IQ-gen VCO MIXER LPF VGA - 13 - CXD2832ER IOUTP/IOUTN BUFFER QOUTP/QOUTN BUFFER ...
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Serial Bus Interface Block The internal registers of this IC are set via the 2-wire serial bus. Registers that can be set via the bus have an 8-bit sub address, and this IC uses the sub addresses 00h ...
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... Connection of resistor Connect to GND Connect to GND via R EXT Connect to GND via R EXT Connect to PLLREG Connect to V via R DD EXT (in case 2 Connect to V via R DD EXT (in case 3 CXD2832ER Recommended value of R [] EXT 0 10k 47k 0 22k or 33k 47k or 68k ...
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... Slave Address DATA Start Condition Sr: Repeated Start Condition P: Stop Condition A: Acknowledge W: W/R Bit = "0" Write Mode R: W/R Bit = "1" Read Mode HD:STA t t SU:STA HIGH Repeatd Start - 16 - CXD2832ER DATA DATA1 BUF t SU:STO Stop Start ...
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Detailed Description of Registers The data noted for each register are the initial values for this IC. Sub Register name address 00 P_COUNT_H[7:0] P_COUNT_L[3:0] 01 S_COUNT[2:0] RESERVE 02 K_COUNT_H[7:0] 03 K_COUNT_L[7:0] MDIV_SW 04 RESERVE[6:0] CALIB_START 05 RESERVE[6:0] 06 REF_R[7:0] ...
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... Test register Test register Enabler of LNA circuit LNA Disable 1: LNA Enable Enabler of RFVGA circuit RFVGA Disable 1: RFVGA Enable Enabler of regulator for RF circuits RFREG Disable 1: RFREG Enable RESERVE RESERVE - 18 - CXD2832ER Description ...
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... RW 0 Test register RW 0 Test register Test register RESERVE Test register RW 0 Test register RW 1 Test register RW 1 Test register RW 1 Test register RESERVE RESERVE RESERVE - 19 - CXD2832ER Description ...
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... Test register RW 0 RESERVE RW 0 Test register RW 1 Test register Test register RW 0 RESERVE Test register Set to initial value RW 0 Test register Test register Enabler of circuit between VCO and MIXER Enable 0: Disable - 20 - CXD2832ER Description ...
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Sub Register name Bit address VCO_BUF_M_EN VCO_BUF_L_EN VCOBUF_EN DMPS_EN 2A CML2CMOS_EN VCO_FC_CLK_EN IQGEN_EN RESERVE 2B RESERVE[7:0] 2C RESERVE[7:0] GPIO[1:0] 2D MONI_SEL[3:0] RESERVE[1:0] 2E RESERVE[7:0] 2F RESERVE[7:0] RST_L_DTCT LCK_DTCT_CYCLE[ UNLCK_DTCT_CYCL E[1:0] RESERVE[2:0] FREQCTR_START FC_CLK_DIV_TEST[ RESERVE[4:0] 32 FVCO_H[7:0] ...
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Sub Register name Bit address LPF_ADJ_EN 37 LPFADJ_TG_FREQ[5: 0] LPFADJ_MANUAL_E N LPFADJ_MANUAL[7 LPF_CTL[7:0] 3A FREQ_CTR_H[7:0] FREQ_CTR_L[4:0] 3B VCO_CAL_ERR RESERVE[1:0] CAL_FVCO_ENX 3C TEST_SEL[3:0] RESERVE[2:0] CLK1M_SILENT_EN 3D VCO_CLK_REF_SEL RESERVE[5:0] 7E EXTRA1[7:0] VER[3:0] 7F CHIP_TYPE[3:0] Bit position ...
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... RF = fosc/2 = fref ( (1100 RF 2150 MHz) MDIV_SW = 1' Tuning frequency fosc : Oscillation frequency of VCO circuit fref : Reference frequency REF_R should be the value which satisfy the equation below {crystal oscillation frequency}/REF_R = 1 MHz P: Main counter frequency division ratio S: Swallow counter frequency division ratio - 23 - CXD2832ER ...
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Example of Representative Characteristics AGC Characteristic (Tuning 2150 MHz) 120 100 –20 0 0.2 0.4 0.6 0.8 1 AGCIN voltage [V] IQ Amplitude Error 1 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 ...
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... MHz –40 m2 m5: 1550 MHz 0.95 1.05 1.15 1.25 1.35 1.45 1.55 m3 m6: 2150 MHz Ω CXD2832ER LPFADJ_TG_FREQ = 36 LPFADJ_TG_FREQ = 30 LPFADJ_TG_FREQ = 22 LPFADJ_TG_FREQ = 16 LPFADJ_TG_FREQ = 12 LPFADJ_TG_FREQ = 10 LPFADJ_TG_FREQ = 6 RFIN Return Loss LNA Through LNA Through LNA Through m5 LNA ON LNA ON LNA ON 1 ...
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... RFREG µF 17 AREG 18 AGND CXD2832ER 19 AGCIN 20 QOUTN 21 QOUTP CXD2832ER 1 µ 6.8 kΩ 1500 150 µF 0.1 µF PLLREG XTI 4 3 ∗ XTO 1 0 Ω 2 ∗ DGND GPIO ...
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... Package outline (Unit: mm CXD2832ER Sony Corporation ...