cxd3220r Sony Electronics, cxd3220r Datasheet - Page 45
cxd3220r
Manufacturer Part Number
cxd3220r
Description
Ieee1394 Link/transaction Layer Controller Lsi For Sbp-2
Manufacturer
Sony Electronics
Datasheet
1.CXD3220R.pdf
(65 pages)
- Current page: 45 of 65
- Download datasheet (414Kb)
7-2. Transport Data I/F
7-2-1. Data Bus
This data interface is 8 bits/16 bits, and switching is done by accessing the CFR AIDT16 register. (The default
value is 16 bits.)
7-2-2. Transmit Interface
The CXD3220R supports only Asynchronous communication for a single login of one initiator per target. It
does not support communication of multiple transport data with Asynchronous packets. The ADP cannot be
used for simultaneous transmission and reception.
The timing chart for the interface is indicated below.
The restriction on the transport data SDRQ output frequency is 12.288MHz (max.).
Transmit Interface
(1) ENDEC IC
SD15 to 0
XHWR
SDRQ
XSAC
Link IC
Tdlac
0ns
Thrq 30ns min
Thlac
45ns max
Tacwr
0ns
Thwrl
– 45 –
50ns
Tswhd
20ns
Tcycdr
81.4ns
Thwhd
0ns
Twrac
0ns
SD15 to 8 Odd Byte (Byte 1, 3, 5 ······)
SD7 to 0 Even Byte (Byte 0, 2, 4 ······)
CXD3220R
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