ml6692 Microsemi Corporation, ml6692 Datasheet - Page 14

• Manufacturer Part Number: ml6692
• Description: 100base-tx Physical Layer With
• Manufacturer: Microsemi Corporation

ML6692
INITIALIZATION INTERFACE
The ML6692 has an Initialization Interface to allow
register programming that is not supported by the MII
Management Interface. The intitialization data is loaded
at power-up and cannot be changed afterwards. The pin
EDIN selects one of three possible programming modes.
The Initialization Register bit assignment is shown in
Table 1.
EEPROM PROGRAMMING
With EDIN floating (set to a high impedance), the
ML6692 reads the 16 configuration bits from an external
serial EEPROM (93LC46 or similar) using the industry-
standard 3-wire serial I/O protocol. After power up, the
ML6692 automatically generates the address at EDIN and
the clock at ECLK to read out the 16 configuration bits.
The EEPROM generates the configuration bit stream at
EDOUT, synchronized with ECLK. Interface timing is
shown in Figure 6. It is important to note that the ML6692
expects LSBs first, whereas the 93LC46 shifts MSBs out
14
(EEPROM ADDR)
Floating
EDIN
High
Low
(DRIVEN BY
(DRIVEN BY
(DRIVEN BY
ML6692)
ML6692)
EEPROM)
EDOUT
EDIN
ECLK
SB
1
01
Microcontroller
OP1
Hardwired
EEPROM
1
MODE
02
OP0
Figure 7. Microcontroller Mode Interface Timing
0
03
A5
0
t
Figure 6. EEPROM Interface Timing
(INPUT TO
(INPUT TO
04
PW1
ML6692)
ML6692)
EDOUT
A4
ECLK
0
from Microcontroller) from Microcontroller)
ECLK (Output Clock
05
(Initialization bit 9)
ECLK (Input Clock
SEL10FD/ECLK
A3
to EEPROM)
0
SEL10FD
06
01
t
A2
S1
0
t
07
H1
02
t
PW3
t
PW2
first. Therefore, the data pattern must be reversed before
programming it into the EEPROM.
MICROCONTROLLER PROGRAMMING
With EDIN high, the ML6692 expects the 16
configuration bits transfered directly at EDOUT,
synchronized with the first 16 clock rising edges provided
externally at ECLK after power-up. This mode is useful
with a small microcontroller; one controller can program
several ML6692 parts by selectively toggling their ECLK
pins. Interface timing is shown in Figure 7.
ML6692 HARD-WIRED DEFAULT
With EDIN low, the SEL10HD, SEL10FD, and SEL100T4
pins set their corresponding bits in the management status
register, and the ML6692 responds to MII PHYAD 00000
only.
A1
0
08
FUNCTION OF RELATED PINS
A0
0
09
16
EDOUT (Input Data
EDOUT (Input Data
(Initialization bit 8)
SEL100T4/EDOUT
t
t
PW4
PER2
from EEPROM)
10
SEL100T4
D0
t
PER1
11
16 BITS DATA ADDRESS
D1
t
DV1
12
D2
13
D3
(Initialization bit 10)
D14
No Affect
No Affect
SEL10HD
SEL10HD
26
D15