SI2107 SILABS [Silicon Laboratories], SI2107 Datasheet - Page 24

• Manufacturer Part Number: SI2107
• Description: SATELLITE RECEIVER FOR DVB-S/DSS
• Manufacturer: SILABS [Silicon Laboratories]

Si2107/08/09/10
6.4.7. C/N Estimator
A carrier-to-noise estimator is provided to aid in satellite
antenna positioning. The C/N measurement mode bit,
CNM, controls whether the count is performed over a
fixed-length or infinite window. With a fixed-length
window, the window size is defined by register CNW.
Measurements are stored in a 16-bit saturating register,
CNL. Setting the C/N estimator start bit, CNS clears the
CNL register and initiates the C/N measurement. When
operating in the finite window mode, the CNS bit is
automatically cleared when the measurement is
complete. The CNS bit must be cleared manually in the
infinite mode to stop the count. An external lookup table
is used to translate the measurement into a C/N
estimate for a given setting of the C/N threshold, CNET,
and a given digital AGC setting.
6.5. Channel Decoder
6.5.1. Viterbi Decoder
The Viterbi decoder performs maximum likelihood
estimation of convolutional codes in compliance with
DVB-S and DSS standards. When lock is achieved, the
Viterbi lock indicator, VTL, is asserted. If Viterbi lock is
not achieved after exhausting the specified parameter
space, the device declares Viterbi search failure by
asserting the VTF bit. The Viterbi search commences
under the control of the acquisition sequencer.
The device can be programmed to attempt to
automatically acquire Viterbi lock using all, one, or a
subset of the supported code rates using the VTCS
register.
If lock is achieved, the status of the search, including
code rate, puncturing pattern phase, 90-degree phase
rotation, and I/Q swap, can be monitored in the Viterbi
search status registers, VTRS, VTPS, and VTIQS.
6.5.2. Viterbi BER Estimator
The Viterbi BER estimator measures the frequency of
bit errors at the input of the Viterbi decoder. The Viterbi
BER mode bit, VTERM, controls whether the count is to
be performed over a fixed length or infinite window. The
window size is defined by VTERW. The BER count is
stored in a 16-bit saturating register, VTBRC. Setting
the Viterbi BER measurement start bit, VTERS, clears
the VTBRC register and initiates the measurement.
When operating in the finite window mode, the VTERS
bit is automatically cleared when the measurement is
complete. The VTERS bit must be cleared manually in
the infinite mode to stop the count.
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Preliminary Rev. 0.7
6.5.3. Reed-Solomon Error Monitor
The Reed-Solomon error monitor is capable of counting
bit, byte, and uncorrectable packet errors. The error
type to be counted is controlled by the Reed-Solomon
error type register, RSERT. The Reed-Solomon error
mode bit, RSERM, controls whether the count is to be
performed over a fixed length or infinite window. The
window size is defined by RSERW. The BER count is
stored in a 16-bit saturating register, RSERC. Setting
the RS BER measurement start bit, RSERS, clears the
RSERC register and initiates the measurement. When
operating in the finite window mode, the RSERS bit is
automatically cleared when the measurement is
complete. The RSERS bit must be cleared manually in
the infinite mode, to stop the count.
6.5.4. PRBS BER Tester
To facilitate in-system pseudo random bit sequence
(PRBS) BER testing, the device provides the ability to
synchronize and track test sequences contained in the
payload (i.e. not SYNC bytes) of the MPEG data
stream. A PRBS test pattern must be encoded,
modulated, and injected into the channel to be
monitored. The device supports a PRBS 2
long described by the following polynomial:
To enable PRBS testing, the Reed-Solomon error type
register, RSERT, must be appropriately programmed.
After the device has synchronized to the incoming
PRBS test pattern, errors are reported in the RSERC
register.
Measurements can be performed at the output of the
Viterbi or Reed-Solomon decoder. To record errors at
the output of the Viterbi decoder, the Reed-Solomon
decoder and interleaver must be bypassed by setting
RS_BP and DI_BP in the “System Configuration”
section of the register map. To record errors at the
output of the Reed-Solomon block, the RS_BP bit must
be cleared.
6.5.5. Frame Synchronizer
The output of the Viterbi decoder is aligned into bytes by
detecting sync patterns within the data stream. In DVB-
S systems, the sync byte, 47h, occurs during the first
byte of a 204 byte RS code block. In DSS systems, a
sync byte, 1Dh, is appended to the beginning of each
RS encoded 146-byte block, resulting in 147-byte RS
code blocks. In DSS mode, sync bytes are discarded
before the byte stream is output to subsequent
decoding stages. When lock is achieved, the frame
synchronization lock bit, FSL, is asserted. If lock is not
achieved, the frame synchronizer fail bit, FSF, is
asserted.
G x ( )
=
x
23
+
x
18
+
1
23
– 1 bits