SI2404 SILABS [Silicon Laboratories], SI2404 Datasheet - Page 68

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SI2404

Manufacturer Part Number
SI2404
Description
V.90, V.34, V.32BIS, V.22BIS ISOMODEM WITH GLOBAL DAA
Manufacturer
SILABS [Silicon Laboratories]
Datasheet

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Si2457/34/15/04
68
Pin #
10
12
13
14
15
16
17
18
22
23
24
11
SDO/EECLK/D5
SDI/EESD/D2
AOUT/INT
Pin Name
TXD/WR
CTS/CS
DCD/D4
ESC/D3
RESET
INT/D0
RI/D1
C2A
C1A
Transmit Data/Write Enable.
Data input from DTE TXD pin in serial mode. Active low write enable pin in paral-
lel mode.
Clear to Send/Chip Select.
Signals that the Si2457/34/15/04 is ready to receive morre digital data on the
TXD pin in data mode. Active low chip select in parallel mode.
Reset Input.
An active low input that is used to reset all control registers to a defined initialized
state.
Isolation Capacitor 2A.
Connects to one side of the isolation capacitor, C2.
Isolation Capacitor 1A.
Connects to one side of the isolation capacitor, C1.
Analog Output/Interrupt Output.
Analog output in serial mode. Active low interrupt output in parallel mode.
Interrupt Output/Data Bit.
Active low interrupt output in serial mode. Bidirectional parallel bus data bit 0 in
parallel mode.
Ring Indicator/Data Bit.
The RI on (active low) indicates the presence of an ON segment of a ring signal
on the telephone line. Bidirectional parallel bus data bit 1 in parallel mode.
Serial Data In/EEPROM Serial Data Input/Output/Data Bit.
Serial Data In (to codec) output in serial mode. Bidirectional Input/Output to SPI
EEPROM in serial mode when pin 4 is pulled low during power up. Bidirectional
parallel bus data bit 2 in parallel mode.
Escape/Data Bit.
Hardware escape in serial mode. Bidirectional parallel bus data bit 3 in parallel
mode.
Carrier Detect/Data Bit.
Active low carrier detect in serial mode. Bidirectional parallel bus data bit 4 in par-
allel mode.
Serial Data Out/EEPROM Clock/Data Bit 5.
Serial Data Out (from codec) input in serial mode. Clock output for SPI EEPROM
in serial mode when pin 4 is pulled low during power up. Bidirectional parallel bus
data bit 5 in parallel mode.
Rev. 1.0
Description

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