ST72T331 STMICROELECTRONICS [STMicroelectronics], ST72T331 Datasheet - Page 36

• Manufacturer Part Number: ST72T331
• Description: 8-BIT MCU WITH 8 TO 16K OTP/EPROM, 256 EEPROM, 384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST72E331 ST72T331
EEPROM (Cont’d)
5.2.4 Low Power Modes
5.2.5 Interrupts
Note: This event generates an interrupt if the corresponding Enable Control Bit is set and the I-bit in the
CC register is reset (RIM instruction).
5.2.6 Register Description
EEPROM CONTROL REGISTER (CR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:3 = Reserved, forced by hardware to 0.
Bit 2 = E2ITE: Interrupt enable.
This bit is set and cleared by software. It enables the
Data EEPROM interrupt capability when the
E2PGM bit is cleared by hardware. The interrupt re-
quest is automatically cleared when the software
enters the interrupt routine.
0: Interrupt disabled
1: Interrupt enabled
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36
Mode
WAIT
HALT
End of Programming Cycle
7
0
0
The EEPROM can enter WAIT mode on execution of the WFI instruction of the microcontroller.
The EEPROM will immediately enter this mode if there is no programming in progress, other-
wise the EEPROM will finish the cycle and then enter WAIT mode.
The EEPROM immediately enters HALT mode if the microcontroller executes the HALT in-
struction. Therefore the EEPROM will stop the function in progress, and data may be corrupt-
ed.
Description
The EEPROM interrupt exits from Wait mode.
0
0
0
E2ITE
Interrupt Event
E2LAT
E2PGM
0
Bit 1 = E2LAT: Read/Write mode.
This bit is set by software. It is cleared by hard-
ware at the end of the programming cycle. It can
only be cleared by software if E2PGM=0.
0: Read mode
1: Write mode
Bit 0 = E2PGM: Programming Control.
This bit is set by software to begin the program-
ming cycle. At the end of the programming cycle,
this bit is cleared by hardware and an interrupt is
generated if the E2ITE bit is set.
0: Programming finished or not started
1: Programming cycle is in progress
Note: if the E2PGM bit is cleared during the pro-
gramming cycle, the memory data is not guaran-
teed.
E2PGM
Event
Flag
Control
Enable
E2ITE
Bit
from
Wait
Exit
Yes
from
Halt
Exit
No