32C408BRPFB-20 MAXWELL [Maxwell Technologies], 32C408BRPFB-20 Datasheet

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32C408BRPFB-20

Manufacturer Part Number
32C408BRPFB-20
Description
4 Megabit (512K x 8-Bit) SRAM
Manufacturer
MAXWELL [Maxwell Technologies]
Datasheet
F
• 512k x 8-bit CMOS architecture
• R
• Total dose hardness:
• Single event effect:
• Package:
• Fast propagation time:
• Single 5V + 10% power supply
• Low power dissipation:
• TTL compatible inputs and outputs
• Fully static operation
• Three state outputs
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
I/O3
I/O4
I/O1
I/O2
WE
CS
Vcc
Vss
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
EATURES
ation
- > 100 krad (Si), depending upon space mission
- SEL
- SEU
- SEU saturated cross section: 6E-9 cm
-36 pin R
-20, 25, 30 ns maximum access time
- Standby: 60mA (TTL); 10mA (CMOS)
- Operating: 180 mA (20 ns); 170 mA (25 ns); 160 mA (30
- No clock or refresh required
ns)
AD
-P
TH
AK
TH
1
18
: > 68 MeV/mg/cm
® technology hardened against natural space radi-
: < 3MeV/mg/cm
AD
32C408B
-P
:
AK
® flat pack
36
19
2
2
I/O8
I/O7
I/O6
I/O5
A18
A17
A16
A15
Vss
Vcc
A14
A13
A12
A11
A10
OE
NC
NC
2
/bit
DQ0
DQ7
WE
A13
A12
A11
A10
OE
A9
A8
A7
A6
A5
A4
CS
05.02.02 Rev 7
D
Maxwell Technologies’ 32C408B high-speed 4 Megabit SRAM
microcircuit features a greater than 100 krad (Si) total dose
tolerance, depending upon space mission. Using R
packaging technology, the 32C408B realizes higher density,
higher performance and lower power consumption, and is well
suited for high-speed system application. Its fully static design
eliminates the need for external clocks, while the CMOS cir-
cuitry reduces power consumption and provides higher reli-
ability. The 32C408B is equipped with eight common input/
output lines, chip select and output enable, allowing for
greater system flexibility and eliminating bus contention.
Maxwell Technologies' patented R
ogy incorporates radiation shielding in the microcircuit pack-
age. In a GEO orbit, R
100 krad (Si) total radiation dose tolerance; dependent upon
space mission. The patented radiation-hardened R
technology incorporates radiation shielding in the microcircuit
package. It eliminates the need for box shielding while provid-
ing the required radiation shielding for a lifetime in orbit or a
space mission. This product is available with packaging and
screening up to Class S.
DECODER
CONTROL
4 Megabit (512K x 8-Bit) SRAM
INPUT
ESCRIPTION
DATA
ROW
All data sheets are subject to change without notice
Logic Diagram
:
A18
1024 ROWS x 4096 COLUMNS
AD
A17
-P
MEMORY MATRIX
AK
A16
COLUMN DECODER
can provides true greater than
COLUMN I/O
A15
AD
-P
A14
©2002 Maxwell Technologies
32C408B
AK
A3
packaging technol-
A2
All rights reserved.
A1
AD
A0
AD
-P
-P
DQ0
DQ7
AK
AK
®
1

Related parts for 32C408BRPFB-20

32C408BRPFB-20 Summary of contents

Page 1

A18 A2 A17 A3 A16 A4 A15 OE CS I/O1 I/O8 I/O2 I/O7 32C408B Vcc Vss Vss Vcc I/O3 I/O6 I/O4 I/O5 WE A14 A5 A13 A6 A12 A7 A11 A8 A10 ...

Page 2

Megabit (512K x 8-Bit) SRAM T P ARAMETER Voltage on any pin relative Voltage on V supply relative Power Dissipation Storage Temperature Operating Temperature T ABLE P ARAMETER Supply Voltage Ground Input High ...

Page 3

Megabit (512K x 8-Bit) SRAM T ABLE (V P ARAMETER Read Cycle Time -20 -25 -30 Address Access Time -20 -25 -30 Chip Select Access Time -20 -25 -30 Output Enable to Output Valid -20 -25 -30 Chip Select ...

Page 4

Megabit (512K x 8-Bit) SRAM don’t care. T ABLE (V P ARAMETER Write Cycle Time -20 -25 -30 Chip Select to End of Write -20 -25 ...

Page 5

Megabit (512K x 8-Bit) SRAM T ABLE (V P ARAMETER Write Pulse Width(OE Low) -20 -25 -30 Data to Write Time Overlap -20 -25 -30 End Write to Output Low-Z 1 -20 -25 -30 Data Hold from Write Time ...

Page 6

Megabit (512K x 8-Bit) SRAM IGURE IMING 1. All write cycle timing is referenced from the last valid address to the first transition address write occurs during the overlap of a low CS and ...

Page 7

Megabit (512K x 8-Bit) SRAM IGURE high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address and t are defined ...

Page 8

Megabit (512K x 8-Bit) SRAM F 6. SRAM P IGURE SEU ROTON ROSS ECTION TATIC All data sheets are subject to change without notice 05.02.02 Rev 7 32C408B 8 ©2002 Maxwell Technologies All rights reserved. ...

Page 9

Megabit (512K x 8-Bit) SRAM S YMBOL ® LAT AD AK ACKAGE D IMENSION 0.122 ...

Page 10

Megabit (512K x 8-Bit) SRAM Important Notice: These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these ...

Page 11

Megabit (512K x 8-Bit) SRAM Product Ordering Options Model Number 32C408B -XX Feature Access Time Screening Flow Package Radiation Feature Base Product Nomenclature All data sheets are subject to change without notice 05.02.02 Rev 7 32C408B ...

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