hm5216165 Elpida Memory, Inc., hm5216165 Datasheet - Page 27

• Manufacturer Part Number: hm5216165
• Description: 16 M Lvttl Interface Sdram 512-kword ? 16-bit ? 2-bank
• Manufacturer: Elpida Memory, Inc.

Write command to Read command interval:
Same bank, same ROW address: When the read command is executed at the same ROW address of the
same bank as the preceding write command, the read command can be performed after an interval of no less
than 1 cycle. However, in the case of a burst write, data will continue to be written until one cycle before the
read command is executed.
WRITE to READ Command Interval (1)
WRITE to READ Command Interval (2)
Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot
be executed; it is necessary to separate the two commands with a precharge command and a bank-active
command.
Different bank: When the bank changes, the read command can be performed after an interval of no less
than 1 cycle, provided that the other bank is in the bank-active state. However, in the case of a burst write,
data will continue to be written until one cycle before the read command is executed (as in the case of the
same bank and the same address).
DQMU/DQML
DQMU/DQML
Command
Command
Dout
CLK
Dout
Din
CLK
Din
WRIT
Column=A
in A0
Write
Column=A
WRIT
Write
in A0
Data Sheet E0167H10
in A1
READ
Column=B
Read
CAS Latency
READ
Column=B
Read
CAS Latency
Column=B
Dout
out B0
Column=B
Dout
out B0
out B1
out B1
out B2
out B2
out B3
HM5216165 Series
out B3
Burst Write Mode
CAS Latency = 1
Burst Length = 4
Bank0
Burst Write Mode
CAS Latency = 1
Burst Length = 4
Bank0
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