hd66727 Renesas Electronics Corporation., hd66727 Datasheet
hd66727
Related parts for hd66727
hd66727 Summary of contents
Page 1
... LCD drive bleeder- resistors. Combining these hardware functions with software functions such as standby and sleep modes allows a fine power control. The HD66727, with the above functions, is suitable for any portable battery- driven product requiring long-term driving capabilities and small size. ...
Page 2
... HD66727 11,520-bit character generator ROM 240 characters (6 8 dots) 32 6-bit character generator RAM 4 characters (6 8 dots) 8 6-bit segment RAM 40 segment-icons and marks max 60-segment 34-common liquid crystal display driver Programmable display sizes and duty ratios (see Table 1) Vertical smooth scroll Vertical double-height display of all character fonts ...
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... Type Name External Type Name Dimension HD66727A03TA0L TCP HCD66727A03 Bare chip HCD66727A03BP Au-bumped chip HD66727A04TA0L TCP HCD66727A04 Bare chip HCD66727A04BP Au-bumped chip Operation Voltage Internal Font 2.4V to 5.5V Japanese and European fonts 2.4V to 5.5V PHS & Pager fonts HD66727 3 ...
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... HD66727 LCD-II Family Comparison LCD-II Item (HD44780U) Power supply voltage 2.7V to 5.5V Liquid crystal drive 3.0 to 11.0V voltage Maximum display - 8 characters characters per chip 2 lines Segment display None Display duty ratio 1/8, 1/11, and 1/16 CGROM 9,920 bits (208 5- -8 dot characters and 32 5- -10 dot characters) CGRAM 64 bytes ...
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... Dot (raster-row) unit Dot (raster-row) unit Standby mode and Standby mode and sleep mode sleep mode serial bits clock-synchronized serial Slim chip with/without bumps Slim chip with/without bumps TCP TCP HD66727 30% 30% 30% 30% 5 ...
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... HD66727 HD66727 Block Diagram RESET* TEST Instruction register (I R) LED0– LED2 LED output PORT0– 8 port PORT2 IM Serial ID0 interface Busy • I2C bus flag ID1/CS* (BF) • Clock synchro- SCL 8 nized Data SDA register serial (DR) 4 Key scan KIN0– ...
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... HD66727 Pad Coordinates Pad X Y Pad No. Name No. Name — DUM1 –5446 –1244 46 KIN1 1 V –5146 –1244 47 KIN2 –5022 –1244 48 KIN3 –4898 –1244 49 KST0 CC — DUM2 –4648 –1244 50 KST1 — DUM3 –4524 –1244 51 KST2 4 V1OUT –4336 –1169 52 KST3 5 V2OUT –4216 – ...
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... HD66727 HD66727 Pad Arrangement Chip size: 11.39 m 2.89 m Pad coordinates: Pad center Coordinate origin: Chip center Pad pitch: 120 m Al pad size bump size DUM1 DUM2 DUM3 V1OUT V2OUT V3OUT V4OUT V5OUT VREFP VREF VREFM ...
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... KIN2 KIN3 KIN3 KST0 KST0 KST1 KST1 KST2 KST2 KST3 KST3 KST4 KST4 KST5 KST5 KST6 KST6 KST7 KST7 IRQ* IRQ* LED0 LED0 LED1 LED1 LED2 LED2 PORT0 PORT0 PORT1 PORT1 PORT2 PORT2 GND GND GND AGND Dummy LCD Glass HD66727 9 ...
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... HD66727 TCP Dimensions V V1OUT V2OUT V3OUT V4OUT V5OUT VREFP VREF VREFM V V5OUT3 V5OUT2 Vci GND V OSC2 OSC1 EXM OPOFF TEST I/O and power supply RESET* ID0 0.60P (51-1) ID1/CS* = 30.0 mm SCL SDA KIN0 KIN1 KIN2 KIN3 KST0 KST1 KST2 KST3 KST4 KST5 KST6 KST7 ...
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... HD66727 Mounting Variations and Key-Matrix Configurations (1) COB-1 (2) COB-2 LCD glass COB board Chip Heat seal Key-matrix board Key-matrix board Figure 1 HD66727 Mounting Variations Table 2 Configurations of LCD Modules (LCM) with Key Scan Function for Different Mounting ...
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... Selects the HD66727 in the clock-synchronized serial mode: Low: HD66727 is selected and can be accessed High: HD66727 is not selected and cannot be accessed Inputs/outputs serial (receive/transmit) data and outputs the acknowledge bit in the I Inputs/outputs serial (receive/transmit) data in the clock- synchronized serial mode. ...
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... GND power supply for LCD drive +2.4V to +5.5V; GND (logic Low level power supply for annunciator display; can adjust contrast of annunciators; AGND For R-C oscillation, connect an external resistor. For external clock supply, input clock pulses to OSC1. HD66727 level. CC – V 13V. EE GND. 13 ...
Page 14
... HD66727 Table 3 Pin Functional Description (cont) Number of Signal Pins I/O Connected to Vci 2 I Power supply V5OUT2 capacitance V5OUT3 C1 — Booster capacitance RESET MPU or external R-C circuit EXM 1 I MPU OPOFF dummy 2 0 Input pad CC TEST ...
Page 15
... DR read as an internal operation (DDRAM, CGRAM, or SEGRAM to DR) Busy Flag (BF) When the busy flag is 1, the HD66727 is in the internal operation mode, and the next instruction will not be accepted. When and R the busy flag is output from DB7. The next instruction must be written after ensuring that the busy flag data must be transferred in appropriate timing considering instruction execution times ...
Page 16
... The key matrix scanner senses and holds the key states at each rising edge of the key strobe signals that are output by the HD66727. The key strobe signals are output as time-multiplexed signals from KST0 to KST7. After passing through the key matrix, these strobe signals are used to sample the key status on four inputs KIN0 to KIN3, enabling keys to be scanned ...
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... It HD66727 9th 10th ...
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... HD66727 Table 7 Relation between Character Codes and Character Patterns (ROM code: A03) Lower Upper CGRAM CGRAM CGRAM CGRAM CGRAM CGRAM 0 y (1) (2) (3) (4) ( ...
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... CGRAM CGRAM CGRAM CGRAM CGRAM CGRAM (2) (3) (4) (1) (2) (3) HD66727 CGRAM CGRAM CGRAM CGRAM (4) (1) (2) (3) (4) 19 ...
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... HD66727 Character Generator RAM (CGRAM) Character generator RAM (CGRAM case of 6 8-dot characters four characters may be redefined. Write the character codes at addresses “00”H to “03”H into DDRAM to display the character patterns stored in CGRAM (Table 8). Table 8 Example of Relationships between Character Code (DDRAM) and Character Pattern ...
Page 21
... SEG47 SEG48 * SEG11, SEG12, SEG13, SEG31, SEG32, SEG33, SEG51 SEG52 SEG53 * SEG16, SEG17, SEG18, SEG36, SEG37, SEG38, SEG56 SEG57 SEG58 HD66727 Common D1 D0 Signal SEG4, SEG5, COMS1 SEG24, SEG25, SEG44 SEG45 SEG9, SEG10, COMS1 SEG29, SEG30, SEG49 SEG50 SEG14, SEG15, COMS1 ...
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... HD66727 Table 10 Correspondence between Segment Display SEGRAM Addresses (ASEG) and Driver Signals in the 6-Dot Font Width ASEG Address Segment Signals MSB LSB SEG1, SEG25, SEG49 SEG7, SEG31, SEG55 SEG13, SEG37 SEG19, SEG43 ...
Page 23
... Tables illustratate the correspondence between the annunciator addresses (AAN) and driver signals Cursor position level, halting display. to AGND), the LCD drive power supply circuit is not CC HD66727 Display position DDRAM address CC 23 ...
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... HD66727 Table 11 Correspondence between Annunciator Display Addresses (AAN) and Driver Signals AAN Address Annunciator Segment Signals MSB LSB ASEG1 Blink Data ASEG5 Blink Data ASEG9 Blink Data Notes: 1. The annunciator is turned on when the corresponding even bit (data and is turned off when ...
Page 25
... LED Output Port The HD66727 includes three LED/back-light driving output ports and three general output ports. These ports can control the LED from the microcomputer through the serial interface. Booster (DC-DC Converter) The booster doubles or triples a voltage input to the Vci pin. With this function, both the internal logic units and LCD drivers can be controlled with a single power supply ...
Page 26
... HD66727 Modifying Character Patterns Character pattern development procedure User Start Determine character patterns Create EPROM address data listing Write EPROM EPROM Hitachi Evaluate character patterns Sample evaluation Figure 4 Character Pattern Development Procedure 26 Hitachi Computer processing Create character pattern listing ...
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... If there are no problems within the character pattern listing, a trial LSI is created at Hitachi and samples are sent to the user for evaluation. When it is confirmed by the user that the character patterns are correctly written, mass production of the LSI will proceed at Hitachi. HD66727 27 ...
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... EPROM data in CGRAM area: Always fill with zeros. 3. Treatment of unused user patterns in the HD66727 EPROM: According to the user application, these are handled in either of two ways: a. When unused character patterns are not programmed unused character code is written into DDRAM, all its dots are lit, because the EPROM is filled with 1s after it is erased ...
Page 29
... Instructions Outline Only the instruction register (IR) and the data register (DR) of the HD66727 can be controlled by the MPU. Before starting internal operation of the HD66727, control information is temporarily stored in these registers to allow interfacing with various peripheral control devices or MPUs which operate at different speeds. The internal operation of the HD66727 is determined by signals sent from the MPU. These signals, which include register selection bit (RS), read/write bit (R/W), and the data bus (DB0 to DB7), make up the HD66727 instructions ...
Page 30
... HD66727 Instruction Description Busy Flag/Key Scan Read The busy flag/key scan read instruction (Figure 5) reads scan data SD3 to SD0 latched into scan registers SCAN0 to SCAN7, scan cycle state SF1 and SF0, and transfer flag TF, sequentially. It also reads the busy flag (BF) indicating that the system is now internally operating on a previously received instruction the internal operation is in progress ...
Page 31
... The cursor and blinking can be set to display simultaneously. When LC and the blinking is displayed as switching between all white dots and displayed characters. Figure 11 shows cursor control examples. DB0 DB0 I/D OSC HD66727 1 31 ...
Page 32
... Cursor mode can be selected with the B/W, C, and B bits. Refer to the Line-Cursor Display section. RS R/W DB7 0 0 Figure 12 Display On/Off Control Instruction 32 DB0 B Alternating display (every 32 frames) Alternating display ii) Blink display example level and off. Because of this, the HD66727 can control charging CC DB0 ...
Page 33
... EXM pin. When the annunciator display is not needed, make sure to turn off display (DA = 0). Normal key scanning is also halted in the standby mode. However, the HD66727 can detect four key inputs connected with strobe signal KST0, thus generating the key scan interrupt (IRQ*). For details, refer to the Standby Mode section and the Key Scan Interrupt section ...
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... HD66727 During the standby mode, the other RAM data and instructions may be lost; they must be set again after the standby mode is canceled. RS R/W DB7 0 0 Figure 13 Power Control Instruction Display Control The display control instruction (Figure 14) includes the NL and DL bits. NL1, NL0: Designates the number of display lines. This value determines the LCD drive multiplexing duty ratio (Table 15). The address assignment is the same for all display line modes. DL3– ...
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... DB0 SN2 CT3 CT2 CT1 CT0 HD66727 – – – – – Figure 16 Contrast Adjuster Variable Resistor Value (VR HD66727 35 ...
Page 36
... HD66727 Scroll Control The scroll control instruction (Figure 17) includes the SN and SL bits. SN1, SN0: Combined with the SN2 bit described in the Contrast Control section to select the top line to be displayed (display-start line) through the data output from the COM1 pin (Table 17). After first five lines are displayed from the top line, the cycle is repeated and scrolling continues. SL2– ...
Page 37
... The SEGRAM address cannot be set during the sleep or standby mode. AAAA is the address for setting the 0011 LED/general port data; 0100 is the address for setting the SEG/COM shift direction. See 'Annunciator Driver Circuit' for details. RS R/W DB7 0 0 Figure 18 Annunciator/SEGRAM Address Set Instruction DB0 HD66727 37 ...
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... HD66727 Table 19 Annunciator/LED/SEG/COM Shift Direction/SEGRAM Address Set Address DB7 Annunciator ASEG1 address ASEG5 ASEG9 LED port address SEG/COM shift direction address SEGRAM address ...
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... DB0 1 0 IRE KF1 KF0 A A Upper bits Lower bits Invalid Addresses “0C”H to “0F”H “1C”H to “1F”H “2C”H to “2F”H “3C”H to “3F”H “4C”H and subsequent addresses HD66727 39 ...
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... HD66727 IRE: When IRE is 1, the key scan interrupt (IRQ*) generation is enabled. When a key is pressed, the IRQ* pin outputs a low level signal. KF1, KF0: Used for specifying the key scan cycle. Set these bits according to the mechanical characteristics of the keys and the oscillation frequency (Table 22). ...
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... After a read, the address is automatically incremented or decremented by 1 according to the I/D bit setting in the entry mode set instruction. RS R/W DB7 1 1 Figure 22 Read Data from RAM Instruction DB0 DB0 HD66727 41 ...
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... HD66727 Table 23 Instruction List No. Instruction R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description KS Busy flag/key scan read CL Clear display Return home Start oscillator EM Entry mode set CR Cursor control DO Display ...
Page 43
... ADD (lower bits) Sets the initial lower DDRAM address to the address counter. Write data Writes data to DDRAM, CGRAM, SEGRAM, annunciator/LED/gener al port, or SEG/COM shift direction. Read data Reads data from DDRAM, CGRAM, or SEGRAM. HD66727 Execution *1 Cycle ...
Page 44
... Reset Function Initialization by Internal Reset Circuit The HD66727 is internally initialized by RESET* input. During initialization, the system executes the instructions as described below. Here, the busy flag (BF) therefore indicates a busy state (BF = 1), accepting no instruction or RAM data access from the MPU. Here, reset input must be held at least 10 ms. ...
Page 45
... Oscillator output pin (OSC2): Outputs oscillation signal 4. Key strobe pins (KST0 to KST7): Outputs strobe signals at a specified time interval 5. Key scan interrupt pin (IRQ*): Outputs V 6. LED driving port (LED0–LED2): Outputs V 7. General output port (PORT0–PORT2): Outputs GND level level CC level CC level CC level CC HD66727 45 ...
Page 46
... RAM data, or transmits key scan data or RAM data. Having received or transmitted 8-bit data normally, the HD66727 pulls down the ninth bit (ACK low level. Therefore, if the ACK is not returned, the data must be transferred again. Multiple bytes of data can be consecutively transferred until the transfer-end condition is satisfied ...
Page 47
... I C bus system * Transfer A6 start 2 HD66727 * Transfer 0 start Notes: 1. Bits the first byte of the I 2. Bits the first byte of the HD66727 indicate the device ID code. Table 25 RS and R/W Bit Function R/W Function 0 0 Writes instruction 0 1 Reads key scan data and BF flag ...
Page 48
... HD66727 a) Basic Data-Receive Timing through the I2C Bus Interface Transfer start SCL (Input) SDA ID1 ID0 (Input/ output) Device ID code RS Slave address 1st byte Acknowledge b) Basic Data-Transmit Timing through the I2C Bus Interface Transfer start ...
Page 49
... ID0 pin. The upper five bits must be 01110. Two different chip addresses must be assigned to a single HD66727 because the seventh bit of the start byte is used as a register select bit (RS): when instruction can be issued or key scan data can be read, and when data can be written to or read from RAM ...
Page 50
... Instruction, RAM data, key-scanned data Instruction 1 Instruction 2 Instruction 1 execution time Adjust the transfer rate so that the HD66727 can complete instruction 1 before the 8th bit of instruction 2 is transferred. Transfer end 16 LSB Instruction 3 Instruction 2 End ...
Page 51
... The generation cycle and pulse width of the key strobe signals depend on the operating frequency (oscillation frequency) of the HD66727, the display line determined by the NL1 bit, and the key scan cycle determined by the KF0 and KF1 bits. For example, when the operating frequency is 160 kHz, NL1 is 1, and KF0 and KF1 are both 0, the generation cycle is 8 ...
Page 52
... HD66727 SCAN0 D03 SCAN1 D13 SCAN2 D23 SCAN3 D33 SCAN4 D43 SCAN5 D53 SCAN6 D63 SCAN7 D73 Figure 26 Key Scan Register Configuration KST0 KST1 KST2 KST3 KST4 KST5 KST6 KST7 Figure 27 Key Strobe Output Timing (NL1 = 1, KF1/0 = 10, fcp/fosc = 160 kHz) 52 KIN3 KIN2 KIN1 KIN0 ...
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... Also, if the transfer flag is read as 1, the HD66727 has been read out while it is latching scan data and is thus unstable; it should also be reconfirmed as required. ...
Page 54
... HD66727 a) Scan Data Read Timing through Clock-Synchronized Serial Bus Interface Transfer start CS* (Input SCL (Input) SDA (Input/ output) Device ID code Start byte b) Scan Data Read Timing through I2C Bus Interface Transfer start SCL (Input) SDA ...
Page 55
... Key Scan Interrupt (Wake-Up Function) If the interrupt enable bit (IRE) is set to 1, the HD66727 sends an interrupt signal to the MPU on detecting that a key has been pressed in the key scan circuit by setting the IRQ* output pin to a low level. An interrupt signal can be generated by pressing any key in a 32-key matrix. The interrupt level continues to be output during the key scan cycle in which the key is being pressed ...
Page 56
... Turn off LCD power (AMP = 0) Set standby mode (STB = 1) Enable interrupts (IRE = 1) Key input (key Generate interrupt (HD66727 MPU) Start R-C oscillator (HD66727) Wait longer (MPU) Mask interrupts (IRE = 0) Clear standby mode (STB = 0) Read key-scanned data (2) Standby Mode Standby mode HD66727) ...
Page 57
... Oscillator Circuit The HD66727 can either be supplied with operating clock pulses externally (external clock mode) or oscillate using an internal R-C oscillator and an external oscillator-resistor (internal oscillation mode), as shown in Figure 31. An appropriate oscillator-resistor must be used to obtain the optimum clock frequency according to the number of display lines (Table 29). Instruction execution times change in proportion to the operating clock frequency or R-C oscillation frequency ...
Page 58
... HD66727 1-line selection period COM1 COM2 COMS2 COMS1 frame Figure 32 LCD Drive Output Waveform Example (4-line display with 1/34 multiplexing duty ratio frame 33 34 ...
Page 59
... Figure 33. Here, contrast can be adjusted through the CT bits of the contrast control instruction. The HD66727 incorporates a voltage-follower operational amplifier for each reduce current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive voltages. Thus, potential differences between V Note that the OPOFF pin must be grounded when using the operational amplifiers ...
Page 60
... V1OUT to V5OUT and V operational amplifier output. Figure 33 External Power Supply Circuit Example for LCD Drive Voltage Generation 60 HD66727 LCD multiplexing driver LCD static driver HD66727 LCD multiplexing driver LCD static driver and V1 and between V5 and SEG1–SEG60 COM1– ...
Page 61
... In this case, Vci must be equal to or smaller than the V The HD66727 incorporates a voltage-follower operational amplifier for each reduce current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive voltages ...
Page 62
... Polarized capacitors must be connected correclty. 6. Circuits for temperature compensation should be designed based on the sample circuit shown in figure 35. 7. The HD66727's internal operational amplifiers have a reduced drive current to save current consumption; when the internal operational amplifiers cannot fully drive the LCD panel used, an appropriate capacitor must be inserted between each output of V1OUT to V5OUT and V (Figure 36) ...
Page 63
... Example of Using Internal Operational Amplifier when Driving Large Size of LCD The driving current of the internal operational amplifier in the HD66727 is reduced to control the consumption current. When load current is apparently large such as when driving large size of LCD panel, insert a capacitor between V1OUT–V5OUT outputs and V the operational amplifier ...
Page 64
... HD66727 When 1/10, 1/18-duty drive *2 LCD driving current ( line, 2 lines) EE When Capacitors for V1OUT to V5OUT EE must be inserted. When Capacitors for V1OUT and V4OUT EE must be inserted. When Capacitors for V1OUT and V4OUT EE may be inserted after confirming the display quality. ...
Page 65
... OPOFF = V CC HD66727 – V1OUT + R V2 – V2OUT V3OUT – V4OUT – V5OUT – Vci C1 0. Booster V5OUT2 0. GND V5OUT3 0. Generation HD66727 level to CC and V5OUT or Vci 65 ...
Page 66
... R through 6 where reference resistance obtained by dividing the total resistance between V The HD66727 incorporates a voltage-follower operational amplifier for each reduce current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive voltages ...
Page 67
... V2 – – – – Figure 38 Contrast Adjuster CT0 Variable Resistor Value (VR 0.4 R HD66727 and AGND. The AGND pin CC 67 ...
Page 68
... HD66727 LCD Panel Interface The HD66727 can change the shift direction of common drivers COM1–COM32 and COMS1 and COMS2 and segment drivers SEG1–SEG60 with the CMS and SGS bits. These bits can be selected according to the mounting method such as the chip arrangement or wire leading. However, the output position of annunciator drivers ASEG1– ...
Page 69
... Segment Display and Annunciator Display The HD66727 provides both segment display, which is driven by the multiplexing method, and annunciator display, which is driven statically. Annunciator display is driven at a logic operating voltage (V AGND) and is thus also available while the LCD drive power supply is turned off. Accordingly, annunciator display is suitable for displaying marks during system standby, when it is desirable to reduce current consumption ...
Page 70
... HD66727 Table 32 Correspondence between Segment Display SEGRAM Addresses (ASEG) and Driver Signals when 5-Dot Font Width ASEG Address Common MSB LSB Signal COMS1 COMS1 COMS1 COMS1 COMS2 COMS2 ...
Page 71
... ASEG10 ASEG11 V level CC AGND level V level CC AGND level V level CC AGND level 1 frame 1 frame V level CC AGND level V level CC AGND level V level CC AGND level V level CC AGND level HD66727 Bits 1, 0 ASEG4 ASEG8 ASEG12 Display off Display on Display off Display on or GND level CC 71 ...
Page 72
... HD66727 Vertical Smooth Scroll The HD66727 can scroll in the vertical direction in units of raster-rows. This function is achieved by writing character codes into DDRAM area that is not being used for display. In other words, since DDRAM corresponds to a 5-line 12-character display, one of the lines can be used to achieve continuous smooth vertical scroll even in a 4-line display ...
Page 73
... SL2–SL0 = 101 7) 6 raster-rows scrolled up · SL2–SL0 = 110 8) 7 raster-rows scrolled up · SL2–SL0 = 111 Figure 41 Example of Vertical Smooth Scrolling HD66727 9) 8 raster-rows scrolled up · SN2–SN0 = 001 · SL2–SL0 = 000 Update the first line of DDRAM data 10) 9 raster-rows scrolled up · ...
Page 74
... HD66727 Scroll up display R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Set initial character codes of 5 lines to all DDRAM addresses CPU Wait CPU Wait ...
Page 75
... Line-Cursor Display The HD66727 can assign a cursor attribute to an entire line corresponding to the address counter value by setting the LC bit to 1 (Table 35). One of three line-cursor modes can be selected: a black-white inverting blink cursor (B/W = 1), an underline cursor (C = 1), and a blink cursor (B = 1). The blink cycle for a black- white inverting cursor and for a blink cursor is 32 frames ...
Page 76
... HD66727 Figure 43 Example of Black-White Inverting Blink Cursor ( B Alternates every 32 frames ...
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... Figure 44 Example of Underline Cursor ( HD66727 77 ...
Page 78
... HD66727 Figure 45 Example of Blink Cursor ( Alternates every 32 frames ...
Page 79
... Double-Height Display The HD66727 can double the height of any desired line from the first to third lines. A line can be selected by the DL3 to DL1 bits as listed in Table 36. All the standard font characters stored in the CGROM and CGRAM can be doubled in height, providing an easy-to-see display. Note that there should be no space between lines for double-height display (Figure 46) ...
Page 80
... HD66727 i) 3-line display example (DL1 = 0, DL2 = 1) 1st line: normal display 2nd line: double-height display ii) 4-line display example ( DL2 = 0, DL3 = 0) 1st line: double-height display 2nd line: normal display 3rd line: normal display Figure 46 Double-Height Display Examples 80 ...
Page 81
... However, when displaying double-width characters with the font in the CGROM, a special double-width font is needed. In that case, a custom ROM is used. Double-height characters can be displayed by setting the register in combination with the above double- width display. Note: This display can be performed with the custom CGROM. Figure 47 Triple-Width Display Examples HD66727 81 ...
Page 82
... HD66727 LED/Back Light Control The HD66727 has three LED ports to control the LED and back light, which need current driving, and three general ports, which do not need current driving. However, the sink current in the LED port output mA. If the back light or LED needs more current, increase the current width with the transistor. ...
Page 83
... The HD66727 can program the number of display lines (NL bits), divide the internal operating frequency by four (OSC bit), and adjust the display contrast (CT bits). Combining these functions, the HD66727 can turn off the second and/or subsequent lines, displaying only the characters in the first line to reduce internal current consumption (partial-display-off function) ...
Page 84
... HD66727 Figure 49 Example of Partially-Off Display (date and time indicated) 84 Display available (driven with selection level) Display available (driven with selection level) Display unavailable (driven with deselection level) ...
Page 85
... Sleep Mode Setting the sleep mode bit (SLP puts the HD66727 in the sleep mode, where the device halts all the internal display operations except for annunciator display and key scan operations, thus reducing current consumption. Specifically, character and segment displays, which are controlled by the multiplexing drive method, are completely halted ...
Page 86
... HD66727 Standby Mode Setting the standby mode bit (STB puts the HD66727 in the standby mode, where the device stops completely, halting all internal operations including the R-C oscillator, thus further reducing current consumption compared to that in the sleep mode. Specifically, character and segment displays, which are controlled by the multiplexing drive method, are completely halted ...
Page 87
... Using the LSI within the following electrical characteristic limits is strongly recommended for normal operation. If these electrical characteristic conditions are also exceeded, the LSI will malfunction and cause poor reliability. Unit Value V –0.3 to +7.0 V –0.3 to +15 –0 0 –30 to +75 C –55 to +110 HD66727 Notes ...
Page 88
... HD66727 DC Characteristics (V = 2.4 to 5.5V – Item Symbol Min Input high voltage VIH 0.7V Input low voltage VIL –0.3 Input low voltage VIL –0.3 Output high voltage (1) VOH1 0.75V (SDA pin) Output low voltage (1) VOL1 — (SDA pin) Output low voltage (1) V OL1 — ...
Page 89
... 160 kHz OSC — 5.0 V Vci Min Typ Max Unit Test Condition 20 160 350 kHz — — 0.2 s — — 0.2 s 120 160 200 kHz R = 150 HD66727 Notes = 7V Notes Notes ...
Page 90
... HD66727 Clock-Synchronized Serial Interface Timing Item Symbol Serial clock cycle time t SCYC Serial clock high-level width t SCH Serial clock low-level width t SCL Serial clock rise/fall time scr scf Chip select set-up time t CSU Chip select hold time t CH Serial input data set-up time ...
Page 91
... Corresponds to the high output for clock-synchronized serial interface. must be maintained. EE Pins: KST7 to KST0, IRQ PMOS PMOS (Pull-up MOS) NMOS GND V CC PMOS (Input circuit) NMOS (Tri-state output circuit PMOS NMOS GND HD66727 LED2 to LED0, PORT2 to PORT0 V CC PMOS NMOS GND Output enable Output data IM 91 ...
Page 92
... HD66727 8. Applies to resistor values (R ) between power supply pins V COM common signal pins (COM1 to COM32, COMS1, and COMS2), and resistor values (R power supply pins V , V2OUT, V3OUT, V5OUT and segment signal pins (SEG1 to SEG60 This excludes the current flowing through pull-up MOSs and output drive MOSs. ...
Page 93
... Booster characteristics test circuits are shown in Figure 55. ( Double boosting ) V CC Vci V5OUT2 V5OUT3 V EE GND (typ (typ.) CC 300 400 500 600 Figure 54 Internal Oscillation ( Triple boosting ) V CC V5OUT2 V5OUT3 GND Figure 55 Booster HD66727 700 800 Vci ...
Page 94
... HD66727 Referential data VUP2 = V – V5OUT2; VUP3 = V CC (i) Relation between the obtained voltage and input voltage Double boosting VUP2 ( 2.0 3.0 4.0 Vci (V) Vci = V , fcp =160 kHz (ii) Relation between the obtained voltage and temperature Double boosting 9.5 9.0 VUP2 (V) 8.5 8.0 7.5 –60 – ...
Page 95
... Double boosting 9.0 8.5 8.0 VUP2 (V) 7.5 7.0 6.5 6.0 0.5 1.0 0.0 I (mA) O Vci = 180 Load Circuits AC Characteristics Test Load Circuits Data bus : SDA Test Point Triple boosting 8.0 7.0 6.0 VUP3 (V) 5.0 typ. 4.0 3.0 2.0 1.5 2.0 0.0 0.5 Vci = 150 Figure 56 Load Circuit HD66727 typ. 1.0 1.5 2.0 I (mA ...
Page 96
... HD66727 Timing Characteristics Clock-Synchronized Serial Interface Timing Start : S CS* VIL t CSU VIH SCL SDA Figure 57 Clock-Synchronized Serial Interface Input Timing Start : S CS* VIL t CSU VIH SCL VIL t SOD SDA Figure 58 Clock-Synchronized Serial Interface Output Timing 96 t SCYC SCH scf ...
Page 97
... SCLH VIH SCL VIL SCLL Figure 59 I Reset Timing RESET* VIL Restart : Sr VIH VIH VIL t t SDAH SDAS t STAS VIH VIH VIL VIL Bus Interface Timing t RES Figure 60 Reset Timing HD66727 Stop : P VIH VIL VIL t STOPS VIH VIL 97 ...